| MemConfig.py (9836:4411b4e0c03a) | MemConfig.py (10041:fae4550d2103) |
|---|---|
| 1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 175 unchanged lines hidden (view full) --- 184 intlv_low_bit + intlv_bits, 185 intlvBits = intlv_bits, 186 intlvMatch = i) 187 mem_ctrls.append(ctrl) 188 189 system.mem_ctrls = mem_ctrls 190 191 # Connect the controllers to the membus | 1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 175 unchanged lines hidden (view full) --- 184 intlv_low_bit + intlv_bits, 185 intlvBits = intlv_bits, 186 intlvMatch = i) 187 mem_ctrls.append(ctrl) 188 189 system.mem_ctrls = mem_ctrls 190 191 # Connect the controllers to the membus |
| 192 for i in xrange(nbr_mem_ctrls): | 192 for i in xrange(len(system.mem_ctrls)): |
| 193 system.mem_ctrls[i].port = system.membus.master | 193 system.mem_ctrls[i].port = system.membus.master |