| MemConfig.py (12564:2778478ca882) | MemConfig.py (13731:67cd980cb20f) |
|---|---|
| 1# Copyright (c) 2013, 2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 72 unchanged lines hidden (view full) --- 81 # string. 82 doc = inspect.getdoc(cls) 83 if doc: 84 for line in doc_wrapper.wrap(doc): 85 print(line) 86 87def mem_names(): 88 """Return a list of valid memory names.""" | 1# Copyright (c) 2013, 2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 72 unchanged lines hidden (view full) --- 81 # string. 82 doc = inspect.getdoc(cls) 83 if doc: 84 for line in doc_wrapper.wrap(doc): 85 print(line) 86 87def mem_names(): 88 """Return a list of valid memory names.""" |
| 89 return _mem_classes.keys() | 89 return list(_mem_classes.keys()) |
| 90 91# Add all memory controllers in the object hierarchy. 92for name, cls in inspect.getmembers(m5.objects, is_mem_class): 93 _mem_classes[name] = cls 94 95def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size): 96 """ 97 Helper function for creating a single memoy controller from the given --- 112 unchanged lines hidden (view full) --- 210 # byte. This value is based on the locality seen across a large 211 # range of workloads. 212 intlv_size = max(128, system.cache_line_size.value) 213 214 # For every range (most systems will only have one), create an 215 # array of controllers and set their parameters to match their 216 # address mapping in the case of a DRAM 217 for r in system.mem_ranges: | 90 91# Add all memory controllers in the object hierarchy. 92for name, cls in inspect.getmembers(m5.objects, is_mem_class): 93 _mem_classes[name] = cls 94 95def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size): 96 """ 97 Helper function for creating a single memoy controller from the given --- 112 unchanged lines hidden (view full) --- 210 # byte. This value is based on the locality seen across a large 211 # range of workloads. 212 intlv_size = max(128, system.cache_line_size.value) 213 214 # For every range (most systems will only have one), create an 215 # array of controllers and set their parameters to match their 216 # address mapping in the case of a DRAM 217 for r in system.mem_ranges: |
| 218 for i in xrange(nbr_mem_ctrls): | 218 for i in range(nbr_mem_ctrls): |
| 219 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, 220 intlv_size) 221 # Set the number of ranks based on the command-line 222 # options if it was explicitly set 223 if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks: 224 mem_ctrl.ranks_per_channel = opt_mem_ranks 225 226 if opt_elastic_trace_en: 227 mem_ctrl.latency = '1ns' 228 print("For elastic trace, over-riding Simple Memory " 229 "latency to 1ns.") 230 231 mem_ctrls.append(mem_ctrl) 232 233 subsystem.mem_ctrls = mem_ctrls 234 235 # Connect the controllers to the membus | 219 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, 220 intlv_size) 221 # Set the number of ranks based on the command-line 222 # options if it was explicitly set 223 if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks: 224 mem_ctrl.ranks_per_channel = opt_mem_ranks 225 226 if opt_elastic_trace_en: 227 mem_ctrl.latency = '1ns' 228 print("For elastic trace, over-riding Simple Memory " 229 "latency to 1ns.") 230 231 mem_ctrls.append(mem_ctrl) 232 233 subsystem.mem_ctrls = mem_ctrls 234 235 # Connect the controllers to the membus |
| 236 for i in xrange(len(subsystem.mem_ctrls)): | 236 for i in range(len(subsystem.mem_ctrls)): |
| 237 if opt_mem_type == "HMC_2500_1x32": 238 subsystem.mem_ctrls[i].port = xbar[i/4].master 239 # Set memory device size. There is an independent controller for 240 # each vault. All vaults are same size. 241 subsystem.mem_ctrls[i].device_size = options.hmc_dev_vault_size 242 else: 243 subsystem.mem_ctrls[i].port = xbar.master | 237 if opt_mem_type == "HMC_2500_1x32": 238 subsystem.mem_ctrls[i].port = xbar[i/4].master 239 # Set memory device size. There is an independent controller for 240 # each vault. All vaults are same size. 241 subsystem.mem_ctrls[i].device_size = options.hmc_dev_vault_size 242 else: 243 subsystem.mem_ctrls[i].port = xbar.master |