| MemConfig.py (11837:17b37f38944a) | MemConfig.py (12094:81aba95c81f9) |
|---|---|
| 1# Copyright (c) 2013 ARM Limited | 1# Copyright (c) 2013, 2017 ARM Limited |
| 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 137 unchanged lines hidden (view full) --- 147 148 If requested, we make a multi-channel configuration of the 149 selected memory controller class by creating multiple instances of 150 the specific class. The individual controllers have their 151 parameters set such that the address range is interleaved between 152 them. 153 """ 154 | 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 137 unchanged lines hidden (view full) --- 147 148 If requested, we make a multi-channel configuration of the 149 selected memory controller class by creating multiple instances of 150 the specific class. The individual controllers have their 151 parameters set such that the address range is interleaved between 152 them. 153 """ 154 |
| 155 if ( options.mem_type == "HMC_2500_1x32"): | 155 # Mandatory options 156 opt_mem_type = options.mem_type 157 opt_mem_channels = options.mem_channels 158 159 # Optional options 160 opt_tlm_memory = getattr(options, "tlm_memory", None) 161 opt_external_memory_system = getattr(options, "external_memory_system", 162 None) 163 opt_elastic_trace_en = getattr(options, "elastic_trace_en", False) 164 opt_mem_ranks = getattr(options, "mem_ranks", None) 165 166 if opt_mem_type == "HMC_2500_1x32": |
| 156 HMChost = HMC.config_host_hmc(options, system) 157 HMC.config_hmc(options, system, HMChost.hmc_host) 158 subsystem = system.hmc_dev 159 xbar = system.hmc_dev.xbar 160 else: 161 subsystem = system 162 xbar = system.membus 163 | 167 HMChost = HMC.config_host_hmc(options, system) 168 HMC.config_hmc(options, system, HMChost.hmc_host) 169 subsystem = system.hmc_dev 170 xbar = system.hmc_dev.xbar 171 else: 172 subsystem = system 173 xbar = system.membus 174 |
| 164 if options.tlm_memory: | 175 if opt_tlm_memory: |
| 165 system.external_memory = m5.objects.ExternalSlave( 166 port_type="tlm_slave", | 176 system.external_memory = m5.objects.ExternalSlave( 177 port_type="tlm_slave", |
| 167 port_data=options.tlm_memory, | 178 port_data=opt_tlm_memory, |
| 168 port=system.membus.master, 169 addr_ranges=system.mem_ranges) 170 system.kernel_addr_check = False 171 return 172 | 179 port=system.membus.master, 180 addr_ranges=system.mem_ranges) 181 system.kernel_addr_check = False 182 return 183 |
| 173 if options.external_memory_system: | 184 if opt_external_memory_system: |
| 174 subsystem.external_memory = m5.objects.ExternalSlave( | 185 subsystem.external_memory = m5.objects.ExternalSlave( |
| 175 port_type=options.external_memory_system, | 186 port_type=opt_external_memory_system, |
| 176 port_data="init_mem0", port=xbar.master, 177 addr_ranges=system.mem_ranges) 178 subsystem.kernel_addr_check = False 179 return 180 | 187 port_data="init_mem0", port=xbar.master, 188 addr_ranges=system.mem_ranges) 189 subsystem.kernel_addr_check = False 190 return 191 |
| 181 nbr_mem_ctrls = options.mem_channels | 192 nbr_mem_ctrls = opt_mem_channels |
| 182 import math 183 from m5.util import fatal 184 intlv_bits = int(math.log(nbr_mem_ctrls, 2)) 185 if 2 ** intlv_bits != nbr_mem_ctrls: 186 fatal("Number of memory channels must be a power of 2") 187 | 193 import math 194 from m5.util import fatal 195 intlv_bits = int(math.log(nbr_mem_ctrls, 2)) 196 if 2 ** intlv_bits != nbr_mem_ctrls: 197 fatal("Number of memory channels must be a power of 2") 198 |
| 188 cls = get(options.mem_type) | 199 cls = get(opt_mem_type) |
| 189 mem_ctrls = [] 190 | 200 mem_ctrls = [] 201 |
| 191 if options.elastic_trace_en and not issubclass(cls, \ 192 m5.objects.SimpleMemory): | 202 if opt_elastic_trace_en and not issubclass(cls, m5.objects.SimpleMemory): |
| 193 fatal("When elastic trace is enabled, configure mem-type as " 194 "simple-mem.") 195 196 # The default behaviour is to interleave memory channels on 128 197 # byte granularity, or cache line granularity if larger than 128 198 # byte. This value is based on the locality seen across a large 199 # range of workloads. 200 intlv_size = max(128, system.cache_line_size.value) 201 202 # For every range (most systems will only have one), create an 203 # array of controllers and set their parameters to match their 204 # address mapping in the case of a DRAM 205 for r in system.mem_ranges: 206 for i in xrange(nbr_mem_ctrls): 207 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, 208 intlv_size) 209 # Set the number of ranks based on the command-line 210 # options if it was explicitly set | 203 fatal("When elastic trace is enabled, configure mem-type as " 204 "simple-mem.") 205 206 # The default behaviour is to interleave memory channels on 128 207 # byte granularity, or cache line granularity if larger than 128 208 # byte. This value is based on the locality seen across a large 209 # range of workloads. 210 intlv_size = max(128, system.cache_line_size.value) 211 212 # For every range (most systems will only have one), create an 213 # array of controllers and set their parameters to match their 214 # address mapping in the case of a DRAM 215 for r in system.mem_ranges: 216 for i in xrange(nbr_mem_ctrls): 217 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, 218 intlv_size) 219 # Set the number of ranks based on the command-line 220 # options if it was explicitly set |
| 211 if issubclass(cls, m5.objects.DRAMCtrl) and \ 212 options.mem_ranks: 213 mem_ctrl.ranks_per_channel = options.mem_ranks | 221 if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks: 222 mem_ctrl.ranks_per_channel = opt_mem_ranks |
| 214 | 223 |
| 215 if options.elastic_trace_en: | 224 if opt_elastic_trace_en: |
| 216 mem_ctrl.latency = '1ns' 217 print "For elastic trace, over-riding Simple Memory " \ 218 "latency to 1ns." 219 220 mem_ctrls.append(mem_ctrl) 221 222 subsystem.mem_ctrls = mem_ctrls 223 224 # Connect the controllers to the membus 225 for i in xrange(len(subsystem.mem_ctrls)): | 225 mem_ctrl.latency = '1ns' 226 print "For elastic trace, over-riding Simple Memory " \ 227 "latency to 1ns." 228 229 mem_ctrls.append(mem_ctrl) 230 231 subsystem.mem_ctrls = mem_ctrls 232 233 # Connect the controllers to the membus 234 for i in xrange(len(subsystem.mem_ctrls)): |
| 226 if (options.mem_type == "HMC_2500_1x32"): | 235 if opt_mem_type == "HMC_2500_1x32": |
| 227 subsystem.mem_ctrls[i].port = xbar[i/4].master 228 else: 229 subsystem.mem_ctrls[i].port = xbar.master | 236 subsystem.mem_ctrls[i].port = xbar[i/4].master 237 else: 238 subsystem.mem_ctrls[i].port = xbar.master |