| MemConfig.py (11183:276ad9121192) | MemConfig.py (11251:a15c86af004a) |
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| 1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 173 unchanged lines hidden (view full) --- 182 from m5.util import fatal 183 intlv_bits = int(math.log(nbr_mem_ctrls, 2)) 184 if 2 ** intlv_bits != nbr_mem_ctrls: 185 fatal("Number of memory channels must be a power of 2") 186 187 cls = get(options.mem_type) 188 mem_ctrls = [] 189 | 1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 173 unchanged lines hidden (view full) --- 182 from m5.util import fatal 183 intlv_bits = int(math.log(nbr_mem_ctrls, 2)) 184 if 2 ** intlv_bits != nbr_mem_ctrls: 185 fatal("Number of memory channels must be a power of 2") 186 187 cls = get(options.mem_type) 188 mem_ctrls = [] 189 |
| 190 if options.elastic_trace_en and not issubclass(cls, \ 191 m5.objects.SimpleMemory): 192 fatal("When elastic trace is enabled, configure mem-type as " 193 "simple-mem.") 194 |
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| 190 # The default behaviour is to interleave memory channels on 128 191 # byte granularity, or cache line granularity if larger than 128 192 # byte. This value is based on the locality seen across a large 193 # range of workloads. 194 intlv_size = max(128, system.cache_line_size.value) 195 196 # For every range (most systems will only have one), create an 197 # array of controllers and set their parameters to match their 198 # address mapping in the case of a DRAM 199 for r in system.mem_ranges: 200 for i in xrange(nbr_mem_ctrls): 201 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, 202 intlv_size) 203 # Set the number of ranks based on the command-line 204 # options if it was explicitly set 205 if issubclass(cls, m5.objects.DRAMCtrl) and \ 206 options.mem_ranks: 207 mem_ctrl.ranks_per_channel = options.mem_ranks 208 | 195 # The default behaviour is to interleave memory channels on 128 196 # byte granularity, or cache line granularity if larger than 128 197 # byte. This value is based on the locality seen across a large 198 # range of workloads. 199 intlv_size = max(128, system.cache_line_size.value) 200 201 # For every range (most systems will only have one), create an 202 # array of controllers and set their parameters to match their 203 # address mapping in the case of a DRAM 204 for r in system.mem_ranges: 205 for i in xrange(nbr_mem_ctrls): 206 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, 207 intlv_size) 208 # Set the number of ranks based on the command-line 209 # options if it was explicitly set 210 if issubclass(cls, m5.objects.DRAMCtrl) and \ 211 options.mem_ranks: 212 mem_ctrl.ranks_per_channel = options.mem_ranks 213 |
| 214 if options.elastic_trace_en: 215 mem_ctrl.latency = '1ns' 216 print "For elastic trace, over-riding Simple Memory " \ 217 "latency to 1ns." 218 |
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| 209 mem_ctrls.append(mem_ctrl) 210 211 subsystem.mem_ctrls = mem_ctrls 212 213 # Connect the controllers to the membus 214 for i in xrange(len(subsystem.mem_ctrls)): 215 subsystem.mem_ctrls[i].port = xbar.master | 219 mem_ctrls.append(mem_ctrl) 220 221 subsystem.mem_ctrls = mem_ctrls 222 223 # Connect the controllers to the membus 224 for i in xrange(len(subsystem.mem_ctrls)): 225 subsystem.mem_ctrls[i].port = xbar.master |