| MemConfig.py (10524:fff17530cef6) | MemConfig.py (10620:74834c49fbbe) |
|---|---|
| 1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 183 unchanged lines hidden (view full) --- 192 cls = get(options.mem_type) 193 mem_ctrls = [] 194 195 # For every range (most systems will only have one), create an 196 # array of controllers and set their parameters to match their 197 # address mapping in the case of a DRAM 198 for r in system.mem_ranges: 199 for i in xrange(nbr_mem_ctrls): | 1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 183 unchanged lines hidden (view full) --- 192 cls = get(options.mem_type) 193 mem_ctrls = [] 194 195 # For every range (most systems will only have one), create an 196 # array of controllers and set their parameters to match their 197 # address mapping in the case of a DRAM 198 for r in system.mem_ranges: 199 for i in xrange(nbr_mem_ctrls): |
| 200 mem_ctrls.append(create_mem_ctrl(cls, r, i, nbr_mem_ctrls, 201 intlv_bits, 202 system.cache_line_size.value)) | 200 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, 201 system.cache_line_size.value) 202 # Set the number of ranks based on the command-line 203 # options if it was explicitly set 204 if issubclass(cls, m5.objects.DRAMCtrl) and \ 205 options.mem_ranks: 206 mem_ctrl.ranks_per_channel = options.mem_ranks |
| 203 | 207 |
| 208 mem_ctrls.append(mem_ctrl) 209 |
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| 204 system.mem_ctrls = mem_ctrls 205 206 # Connect the controllers to the membus 207 for i in xrange(len(system.mem_ctrls)): 208 system.mem_ctrls[i].port = system.membus.master | 210 system.mem_ctrls = mem_ctrls 211 212 # Connect the controllers to the membus 213 for i in xrange(len(system.mem_ctrls)): 214 system.mem_ctrls[i].port = system.membus.master |