MemConfig.py (10442:cd2daa931a54) | MemConfig.py (10524:fff17530cef6) |
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1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 40 unchanged lines hidden (view full) --- 49# fina; list. A target may be specified as a tuple, in which case the 50# first available memory controller model in the tuple will be used. 51_mem_aliases_all = [ 52 ("simple_mem", "SimpleMemory"), 53 ("ddr3_1600_x64", "DDR3_1600_x64"), 54 ("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"), 55 ("lpddr3_1600_x32", "LPDDR3_1600_x32"), 56 ("wio_200_x128", "WideIO_200_x128"), | 1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 40 unchanged lines hidden (view full) --- 49# fina; list. A target may be specified as a tuple, in which case the 50# first available memory controller model in the tuple will be used. 51_mem_aliases_all = [ 52 ("simple_mem", "SimpleMemory"), 53 ("ddr3_1600_x64", "DDR3_1600_x64"), 54 ("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"), 55 ("lpddr3_1600_x32", "LPDDR3_1600_x32"), 56 ("wio_200_x128", "WideIO_200_x128"), |
57 ("dramsim2", "DRAMSim2") | 57 ("dramsim2", "DRAMSim2"), 58 ("ruby_memory", "RubyMemoryControl") |
58 ] 59 60# Filtered list of aliases. Only aliases for existing memory 61# controllers exist in this list. 62_mem_aliases = {} 63 64 65def is_mem_class(cls): --- 142 unchanged lines hidden --- | 59 ] 60 61# Filtered list of aliases. Only aliases for existing memory 62# controllers exist in this list. 63_mem_aliases = {} 64 65 66def is_mem_class(cls): --- 142 unchanged lines hidden --- |