| MemConfig.py (10146:27dfed4c8403) | MemConfig.py (10442:cd2daa931a54) |
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| 1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 112 unchanged lines hidden (view full) --- 121 for t in target: 122 if t in _mem_classes: 123 _mem_aliases[alias] = t 124 break 125 elif target in _mem_classes: 126 # Normal alias 127 _mem_aliases[alias] = target 128 | 1# Copyright (c) 2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 112 unchanged lines hidden (view full) --- 121 for t in target: 122 if t in _mem_classes: 123 _mem_aliases[alias] = t 124 break 125 elif target in _mem_classes: 126 # Normal alias 127 _mem_aliases[alias] = target 128 |
| 129def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, cache_line_size): 130 """ 131 Helper function for creating a single memoy controller from the given 132 options. This function is invoked multiple times in config_mem function 133 to create an array of controllers. 134 """ 135 136 import math 137 # The default behaviour is to interleave on cache line granularity 138 cache_line_bit = int(math.log(cache_line_size, 2)) - 1 139 intlv_low_bit = cache_line_bit 140 141 # Create an instance so we can figure out the address 142 # mapping and row-buffer size 143 ctrl = cls() 144 145 # Only do this for DRAMs 146 if issubclass(cls, m5.objects.DRAMCtrl): 147 # Inform each controller how many channels to account 148 # for 149 ctrl.channels = nbr_mem_ctrls 150 151 # If the channel bits are appearing after the column 152 # bits, we need to add the appropriate number of bits 153 # for the row buffer size 154 if ctrl.addr_mapping.value == 'RoRaBaChCo': 155 # This computation only really needs to happen 156 # once, but as we rely on having an instance we 157 # end up having to repeat it for each and every 158 # one 159 rowbuffer_size = ctrl.device_rowbuffer_size.value * \ 160 ctrl.devices_per_rank.value 161 162 intlv_low_bit = int(math.log(rowbuffer_size, 2)) - 1 163 164 # We got all we need to configure the appropriate address 165 # range 166 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(), 167 intlvHighBit = \ 168 intlv_low_bit + intlv_bits, 169 intlvBits = intlv_bits, 170 intlvMatch = i) 171 return ctrl 172 |
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| 129def config_mem(options, system): 130 """ 131 Create the memory controllers based on the options and attach them. 132 133 If requested, we make a multi-channel configuration of the 134 selected memory controller class by creating multiple instances of 135 the specific class. The individual controllers have their 136 parameters set such that the address range is interleaved between 137 them. 138 """ 139 140 nbr_mem_ctrls = options.mem_channels 141 import math 142 from m5.util import fatal 143 intlv_bits = int(math.log(nbr_mem_ctrls, 2)) 144 if 2 ** intlv_bits != nbr_mem_ctrls: 145 fatal("Number of memory channels must be a power of 2") | 173def config_mem(options, system): 174 """ 175 Create the memory controllers based on the options and attach them. 176 177 If requested, we make a multi-channel configuration of the 178 selected memory controller class by creating multiple instances of 179 the specific class. The individual controllers have their 180 parameters set such that the address range is interleaved between 181 them. 182 """ 183 184 nbr_mem_ctrls = options.mem_channels 185 import math 186 from m5.util import fatal 187 intlv_bits = int(math.log(nbr_mem_ctrls, 2)) 188 if 2 ** intlv_bits != nbr_mem_ctrls: 189 fatal("Number of memory channels must be a power of 2") |
| 190 |
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| 146 cls = get(options.mem_type) 147 mem_ctrls = [] 148 | 191 cls = get(options.mem_type) 192 mem_ctrls = [] 193 |
| 149 # The default behaviour is to interleave on cache line granularity 150 cache_line_bit = int(math.log(system.cache_line_size.value, 2)) - 1 151 intlv_low_bit = cache_line_bit 152 | |
| 153 # For every range (most systems will only have one), create an 154 # array of controllers and set their parameters to match their 155 # address mapping in the case of a DRAM 156 for r in system.mem_ranges: 157 for i in xrange(nbr_mem_ctrls): | 194 # For every range (most systems will only have one), create an 195 # array of controllers and set their parameters to match their 196 # address mapping in the case of a DRAM 197 for r in system.mem_ranges: 198 for i in xrange(nbr_mem_ctrls): |
| 158 # Create an instance so we can figure out the address 159 # mapping and row-buffer size 160 ctrl = cls() | 199 mem_ctrls.append(create_mem_ctrl(cls, r, i, nbr_mem_ctrls, 200 intlv_bits, 201 system.cache_line_size.value)) |
| 161 | 202 |
| 162 # Only do this for DRAMs 163 if issubclass(cls, m5.objects.DRAMCtrl): 164 # Inform each controller how many channels to account 165 # for 166 ctrl.channels = nbr_mem_ctrls 167 168 # If the channel bits are appearing after the column 169 # bits, we need to add the appropriate number of bits 170 # for the row buffer size 171 if ctrl.addr_mapping.value == 'RoRaBaChCo': 172 # This computation only really needs to happen 173 # once, but as we rely on having an instance we 174 # end up having to repeat it for each and every 175 # one 176 rowbuffer_size = ctrl.device_rowbuffer_size.value * \ 177 ctrl.devices_per_rank.value 178 179 intlv_low_bit = int(math.log(rowbuffer_size, 2)) - 1 180 181 # We got all we need to configure the appropriate address 182 # range 183 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(), 184 intlvHighBit = \ 185 intlv_low_bit + intlv_bits, 186 intlvBits = intlv_bits, 187 intlvMatch = i) 188 mem_ctrls.append(ctrl) 189 | |
| 190 system.mem_ctrls = mem_ctrls 191 192 # Connect the controllers to the membus 193 for i in xrange(len(system.mem_ctrls)): 194 system.mem_ctrls[i].port = system.membus.master | 203 system.mem_ctrls = mem_ctrls 204 205 # Connect the controllers to the membus 206 for i in xrange(len(system.mem_ctrls)): 207 system.mem_ctrls[i].port = system.membus.master |