1# Copyright (c) 2013, 2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39from __future__ import print_function
40
41import m5.objects
42import inspect
43import sys
44import HMC
45from textwrap import TextWrapper
46
47# Dictionary of mapping names of real memory controller models to
48# classes.

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61
62def get(name):
63 """Get a memory class from a user provided class name."""
64
65 try:
66 mem_class = _mem_classes[name]
67 return mem_class
68 except KeyError:
67 print "%s is not a valid memory controller." % (name,)
69 print("%s is not a valid memory controller." % (name,))
70 sys.exit(1)
71
72def print_mem_list():
73 """Print a list of available memory classes."""
74
73 print "Available memory classes:"
75 print("Available memory classes:")
76 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
77 for name, cls in _mem_classes.items():
76 print "\t%s" % name
78 print("\t%s" % name)
79
80 # Try to extract the class documentation from the class help
81 # string.
82 doc = inspect.getdoc(cls)
83 if doc:
84 for line in doc_wrapper.wrap(doc):
83 print line
85 print(line)
86
87def mem_names():
88 """Return a list of valid memory names."""
89 return _mem_classes.keys()
90
91# Add all memory controllers in the object hierarchy.
92for name, cls in inspect.getmembers(m5.objects, is_mem_class):
93 _mem_classes[name] = cls

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220 intlv_size)
221 # Set the number of ranks based on the command-line
222 # options if it was explicitly set
223 if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
224 mem_ctrl.ranks_per_channel = opt_mem_ranks
225
226 if opt_elastic_trace_en:
227 mem_ctrl.latency = '1ns'
226 print "For elastic trace, over-riding Simple Memory " \
227 "latency to 1ns."
228 print("For elastic trace, over-riding Simple Memory "
229 "latency to 1ns.")
230
231 mem_ctrls.append(mem_ctrl)
232
233 subsystem.mem_ctrls = mem_ctrls
234
235 # Connect the controllers to the membus
236 for i in xrange(len(subsystem.mem_ctrls)):
237 if opt_mem_type == "HMC_2500_1x32":
238 subsystem.mem_ctrls[i].port = xbar[i/4].master
239 # Set memory device size. There is an independent controller for
240 # each vault. All vaults are same size.
241 subsystem.mem_ctrls[i].device_size = options.hmc_dev_vault_size
242 else:
243 subsystem.mem_ctrls[i].port = xbar.master