1# Copyright (c) 2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42import HMC
43from textwrap import TextWrapper
44
45# Dictionary of mapping names of real memory controller models to
46# classes.
47_mem_classes = {}
48
49def is_mem_class(cls):
50 """Determine if a class is a memory controller that can be instantiated"""
51
52 # We can't use the normal inspect.isclass because the ParamFactory
53 # and ProxyFactory classes have a tendency to confuse it.
54 try:
55 return issubclass(cls, m5.objects.AbstractMemory) and \
56 not cls.abstract
57 except TypeError:
58 return False
59
60def get(name):
61 """Get a memory class from a user provided class name."""
62
63 try:
64 mem_class = _mem_classes[name]
65 return mem_class
66 except KeyError:
67 print "%s is not a valid memory controller." % (name,)
68 sys.exit(1)
69
70def print_mem_list():
71 """Print a list of available memory classes."""
72
73 print "Available memory classes:"
74 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
75 for name, cls in _mem_classes.items():
76 print "\t%s" % name
77
78 # Try to extract the class documentation from the class help
79 # string.
80 doc = inspect.getdoc(cls)
81 if doc:
82 for line in doc_wrapper.wrap(doc):
83 print line
84
85def mem_names():
86 """Return a list of valid memory names."""
87 return _mem_classes.keys()
88
89# Add all memory controllers in the object hierarchy.
90for name, cls in inspect.getmembers(m5.objects, is_mem_class):
91 _mem_classes[name] = cls
92
93def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
94 """
95 Helper function for creating a single memoy controller from the given
96 options. This function is invoked multiple times in config_mem function
97 to create an array of controllers.
98 """
99
100 import math
101 intlv_low_bit = int(math.log(intlv_size, 2))
102
103 # Use basic hashing for the channel selection, and preferably use
104 # the lower tag bits from the last level cache. As we do not know
105 # the details of the caches here, make an educated guess. 4 MByte
106 # 4-way associative with 64 byte cache lines is 6 offset bits and
107 # 14 index bits.
108 xor_low_bit = 20
109
110 # Create an instance so we can figure out the address
111 # mapping and row-buffer size
112 ctrl = cls()
113
114 # Only do this for DRAMs
115 if issubclass(cls, m5.objects.DRAMCtrl):
116 # Inform each controller how many channels to account
117 # for
118 ctrl.channels = nbr_mem_ctrls
119
120 # If the channel bits are appearing after the column
121 # bits, we need to add the appropriate number of bits
122 # for the row buffer size
123 if ctrl.addr_mapping.value == 'RoRaBaChCo':
124 # This computation only really needs to happen
125 # once, but as we rely on having an instance we
126 # end up having to repeat it for each and every
127 # one
128 rowbuffer_size = ctrl.device_rowbuffer_size.value * \
129 ctrl.devices_per_rank.value
130
131 intlv_low_bit = int(math.log(rowbuffer_size, 2))
132
133 # We got all we need to configure the appropriate address
134 # range
135 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
136 intlvHighBit = \
137 intlv_low_bit + intlv_bits - 1,
138 xorHighBit = \
139 xor_low_bit + intlv_bits - 1,
140 intlvBits = intlv_bits,
141 intlvMatch = i)
142 return ctrl
143
144def config_mem(options, system):
145 """
146 Create the memory controllers based on the options and attach them.
147
148 If requested, we make a multi-channel configuration of the
149 selected memory controller class by creating multiple instances of
150 the specific class. The individual controllers have their
151 parameters set such that the address range is interleaved between
152 them.
153 """
154
155 if ( options.mem_type == "HMC_2500_x32"):
| 1# Copyright (c) 2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42import HMC
43from textwrap import TextWrapper
44
45# Dictionary of mapping names of real memory controller models to
46# classes.
47_mem_classes = {}
48
49def is_mem_class(cls):
50 """Determine if a class is a memory controller that can be instantiated"""
51
52 # We can't use the normal inspect.isclass because the ParamFactory
53 # and ProxyFactory classes have a tendency to confuse it.
54 try:
55 return issubclass(cls, m5.objects.AbstractMemory) and \
56 not cls.abstract
57 except TypeError:
58 return False
59
60def get(name):
61 """Get a memory class from a user provided class name."""
62
63 try:
64 mem_class = _mem_classes[name]
65 return mem_class
66 except KeyError:
67 print "%s is not a valid memory controller." % (name,)
68 sys.exit(1)
69
70def print_mem_list():
71 """Print a list of available memory classes."""
72
73 print "Available memory classes:"
74 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
75 for name, cls in _mem_classes.items():
76 print "\t%s" % name
77
78 # Try to extract the class documentation from the class help
79 # string.
80 doc = inspect.getdoc(cls)
81 if doc:
82 for line in doc_wrapper.wrap(doc):
83 print line
84
85def mem_names():
86 """Return a list of valid memory names."""
87 return _mem_classes.keys()
88
89# Add all memory controllers in the object hierarchy.
90for name, cls in inspect.getmembers(m5.objects, is_mem_class):
91 _mem_classes[name] = cls
92
93def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
94 """
95 Helper function for creating a single memoy controller from the given
96 options. This function is invoked multiple times in config_mem function
97 to create an array of controllers.
98 """
99
100 import math
101 intlv_low_bit = int(math.log(intlv_size, 2))
102
103 # Use basic hashing for the channel selection, and preferably use
104 # the lower tag bits from the last level cache. As we do not know
105 # the details of the caches here, make an educated guess. 4 MByte
106 # 4-way associative with 64 byte cache lines is 6 offset bits and
107 # 14 index bits.
108 xor_low_bit = 20
109
110 # Create an instance so we can figure out the address
111 # mapping and row-buffer size
112 ctrl = cls()
113
114 # Only do this for DRAMs
115 if issubclass(cls, m5.objects.DRAMCtrl):
116 # Inform each controller how many channels to account
117 # for
118 ctrl.channels = nbr_mem_ctrls
119
120 # If the channel bits are appearing after the column
121 # bits, we need to add the appropriate number of bits
122 # for the row buffer size
123 if ctrl.addr_mapping.value == 'RoRaBaChCo':
124 # This computation only really needs to happen
125 # once, but as we rely on having an instance we
126 # end up having to repeat it for each and every
127 # one
128 rowbuffer_size = ctrl.device_rowbuffer_size.value * \
129 ctrl.devices_per_rank.value
130
131 intlv_low_bit = int(math.log(rowbuffer_size, 2))
132
133 # We got all we need to configure the appropriate address
134 # range
135 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
136 intlvHighBit = \
137 intlv_low_bit + intlv_bits - 1,
138 xorHighBit = \
139 xor_low_bit + intlv_bits - 1,
140 intlvBits = intlv_bits,
141 intlvMatch = i)
142 return ctrl
143
144def config_mem(options, system):
145 """
146 Create the memory controllers based on the options and attach them.
147
148 If requested, we make a multi-channel configuration of the
149 selected memory controller class by creating multiple instances of
150 the specific class. The individual controllers have their
151 parameters set such that the address range is interleaved between
152 them.
153 """
154
155 if ( options.mem_type == "HMC_2500_x32"):
|
159 else:
160 subsystem = system
161 xbar = system.membus
162
163 if options.tlm_memory:
164 system.external_memory = m5.objects.ExternalSlave(
165 port_type="tlm",
166 port_data=options.tlm_memory,
167 port=system.membus.master,
168 addr_ranges=system.mem_ranges)
169 system.kernel_addr_check = False
170 return
171
172 if options.external_memory_system:
173 subsystem.external_memory = m5.objects.ExternalSlave(
174 port_type=options.external_memory_system,
175 port_data="init_mem0", port=xbar.master,
176 addr_ranges=system.mem_ranges)
177 subsystem.kernel_addr_check = False
178 return
179
180 nbr_mem_ctrls = options.mem_channels
181 import math
182 from m5.util import fatal
183 intlv_bits = int(math.log(nbr_mem_ctrls, 2))
184 if 2 ** intlv_bits != nbr_mem_ctrls:
185 fatal("Number of memory channels must be a power of 2")
186
187 cls = get(options.mem_type)
188 mem_ctrls = []
189
190 if options.elastic_trace_en and not issubclass(cls, \
191 m5.objects.SimpleMemory):
192 fatal("When elastic trace is enabled, configure mem-type as "
193 "simple-mem.")
194
195 # The default behaviour is to interleave memory channels on 128
196 # byte granularity, or cache line granularity if larger than 128
197 # byte. This value is based on the locality seen across a large
198 # range of workloads.
199 intlv_size = max(128, system.cache_line_size.value)
200
201 # For every range (most systems will only have one), create an
202 # array of controllers and set their parameters to match their
203 # address mapping in the case of a DRAM
204 for r in system.mem_ranges:
205 for i in xrange(nbr_mem_ctrls):
206 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
207 intlv_size)
208 # Set the number of ranks based on the command-line
209 # options if it was explicitly set
210 if issubclass(cls, m5.objects.DRAMCtrl) and \
211 options.mem_ranks:
212 mem_ctrl.ranks_per_channel = options.mem_ranks
213
214 if options.elastic_trace_en:
215 mem_ctrl.latency = '1ns'
216 print "For elastic trace, over-riding Simple Memory " \
217 "latency to 1ns."
218
219 mem_ctrls.append(mem_ctrl)
220
221 subsystem.mem_ctrls = mem_ctrls
222
223 # Connect the controllers to the membus
224 for i in xrange(len(subsystem.mem_ctrls)):
| 160 else:
161 subsystem = system
162 xbar = system.membus
163
164 if options.tlm_memory:
165 system.external_memory = m5.objects.ExternalSlave(
166 port_type="tlm",
167 port_data=options.tlm_memory,
168 port=system.membus.master,
169 addr_ranges=system.mem_ranges)
170 system.kernel_addr_check = False
171 return
172
173 if options.external_memory_system:
174 subsystem.external_memory = m5.objects.ExternalSlave(
175 port_type=options.external_memory_system,
176 port_data="init_mem0", port=xbar.master,
177 addr_ranges=system.mem_ranges)
178 subsystem.kernel_addr_check = False
179 return
180
181 nbr_mem_ctrls = options.mem_channels
182 import math
183 from m5.util import fatal
184 intlv_bits = int(math.log(nbr_mem_ctrls, 2))
185 if 2 ** intlv_bits != nbr_mem_ctrls:
186 fatal("Number of memory channels must be a power of 2")
187
188 cls = get(options.mem_type)
189 mem_ctrls = []
190
191 if options.elastic_trace_en and not issubclass(cls, \
192 m5.objects.SimpleMemory):
193 fatal("When elastic trace is enabled, configure mem-type as "
194 "simple-mem.")
195
196 # The default behaviour is to interleave memory channels on 128
197 # byte granularity, or cache line granularity if larger than 128
198 # byte. This value is based on the locality seen across a large
199 # range of workloads.
200 intlv_size = max(128, system.cache_line_size.value)
201
202 # For every range (most systems will only have one), create an
203 # array of controllers and set their parameters to match their
204 # address mapping in the case of a DRAM
205 for r in system.mem_ranges:
206 for i in xrange(nbr_mem_ctrls):
207 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
208 intlv_size)
209 # Set the number of ranks based on the command-line
210 # options if it was explicitly set
211 if issubclass(cls, m5.objects.DRAMCtrl) and \
212 options.mem_ranks:
213 mem_ctrl.ranks_per_channel = options.mem_ranks
214
215 if options.elastic_trace_en:
216 mem_ctrl.latency = '1ns'
217 print "For elastic trace, over-riding Simple Memory " \
218 "latency to 1ns."
219
220 mem_ctrls.append(mem_ctrl)
221
222 subsystem.mem_ctrls = mem_ctrls
223
224 # Connect the controllers to the membus
225 for i in xrange(len(subsystem.mem_ctrls)):
|