1# Copyright (c) 2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
| 1# Copyright (c) 2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
|
| 42import HMC
|
42from textwrap import TextWrapper
43
44# Dictionary of mapping names of real memory controller models to
45# classes.
46_mem_classes = {}
47
48def is_mem_class(cls):
49 """Determine if a class is a memory controller that can be instantiated"""
50
51 # We can't use the normal inspect.isclass because the ParamFactory
52 # and ProxyFactory classes have a tendency to confuse it.
53 try:
54 return issubclass(cls, m5.objects.AbstractMemory) and \
55 not cls.abstract
56 except TypeError:
57 return False
58
59def get(name):
60 """Get a memory class from a user provided class name."""
61
62 try:
63 mem_class = _mem_classes[name]
64 return mem_class
65 except KeyError:
66 print "%s is not a valid memory controller." % (name,)
67 sys.exit(1)
68
69def print_mem_list():
70 """Print a list of available memory classes."""
71
72 print "Available memory classes:"
73 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
74 for name, cls in _mem_classes.items():
75 print "\t%s" % name
76
77 # Try to extract the class documentation from the class help
78 # string.
79 doc = inspect.getdoc(cls)
80 if doc:
81 for line in doc_wrapper.wrap(doc):
82 print line
83
84def mem_names():
85 """Return a list of valid memory names."""
86 return _mem_classes.keys()
87
88# Add all memory controllers in the object hierarchy.
89for name, cls in inspect.getmembers(m5.objects, is_mem_class):
90 _mem_classes[name] = cls
91
92def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
93 """
94 Helper function for creating a single memoy controller from the given
95 options. This function is invoked multiple times in config_mem function
96 to create an array of controllers.
97 """
98
99 import math
100 intlv_low_bit = int(math.log(intlv_size, 2))
101
102 # Use basic hashing for the channel selection, and preferably use
103 # the lower tag bits from the last level cache. As we do not know
104 # the details of the caches here, make an educated guess. 4 MByte
105 # 4-way associative with 64 byte cache lines is 6 offset bits and
106 # 14 index bits.
107 xor_low_bit = 20
108
109 # Create an instance so we can figure out the address
110 # mapping and row-buffer size
111 ctrl = cls()
112
113 # Only do this for DRAMs
114 if issubclass(cls, m5.objects.DRAMCtrl):
115 # Inform each controller how many channels to account
116 # for
117 ctrl.channels = nbr_mem_ctrls
118
119 # If the channel bits are appearing after the column
120 # bits, we need to add the appropriate number of bits
121 # for the row buffer size
122 if ctrl.addr_mapping.value == 'RoRaBaChCo':
123 # This computation only really needs to happen
124 # once, but as we rely on having an instance we
125 # end up having to repeat it for each and every
126 # one
127 rowbuffer_size = ctrl.device_rowbuffer_size.value * \
128 ctrl.devices_per_rank.value
129
130 intlv_low_bit = int(math.log(rowbuffer_size, 2))
131
132 # We got all we need to configure the appropriate address
133 # range
134 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
135 intlvHighBit = \
136 intlv_low_bit + intlv_bits - 1,
137 xorHighBit = \
138 xor_low_bit + intlv_bits - 1,
139 intlvBits = intlv_bits,
140 intlvMatch = i)
141 return ctrl
142
143def config_mem(options, system):
144 """
145 Create the memory controllers based on the options and attach them.
146
147 If requested, we make a multi-channel configuration of the
148 selected memory controller class by creating multiple instances of
149 the specific class. The individual controllers have their
150 parameters set such that the address range is interleaved between
151 them.
152 """
153
| 43from textwrap import TextWrapper
44
45# Dictionary of mapping names of real memory controller models to
46# classes.
47_mem_classes = {}
48
49def is_mem_class(cls):
50 """Determine if a class is a memory controller that can be instantiated"""
51
52 # We can't use the normal inspect.isclass because the ParamFactory
53 # and ProxyFactory classes have a tendency to confuse it.
54 try:
55 return issubclass(cls, m5.objects.AbstractMemory) and \
56 not cls.abstract
57 except TypeError:
58 return False
59
60def get(name):
61 """Get a memory class from a user provided class name."""
62
63 try:
64 mem_class = _mem_classes[name]
65 return mem_class
66 except KeyError:
67 print "%s is not a valid memory controller." % (name,)
68 sys.exit(1)
69
70def print_mem_list():
71 """Print a list of available memory classes."""
72
73 print "Available memory classes:"
74 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
75 for name, cls in _mem_classes.items():
76 print "\t%s" % name
77
78 # Try to extract the class documentation from the class help
79 # string.
80 doc = inspect.getdoc(cls)
81 if doc:
82 for line in doc_wrapper.wrap(doc):
83 print line
84
85def mem_names():
86 """Return a list of valid memory names."""
87 return _mem_classes.keys()
88
89# Add all memory controllers in the object hierarchy.
90for name, cls in inspect.getmembers(m5.objects, is_mem_class):
91 _mem_classes[name] = cls
92
93def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
94 """
95 Helper function for creating a single memoy controller from the given
96 options. This function is invoked multiple times in config_mem function
97 to create an array of controllers.
98 """
99
100 import math
101 intlv_low_bit = int(math.log(intlv_size, 2))
102
103 # Use basic hashing for the channel selection, and preferably use
104 # the lower tag bits from the last level cache. As we do not know
105 # the details of the caches here, make an educated guess. 4 MByte
106 # 4-way associative with 64 byte cache lines is 6 offset bits and
107 # 14 index bits.
108 xor_low_bit = 20
109
110 # Create an instance so we can figure out the address
111 # mapping and row-buffer size
112 ctrl = cls()
113
114 # Only do this for DRAMs
115 if issubclass(cls, m5.objects.DRAMCtrl):
116 # Inform each controller how many channels to account
117 # for
118 ctrl.channels = nbr_mem_ctrls
119
120 # If the channel bits are appearing after the column
121 # bits, we need to add the appropriate number of bits
122 # for the row buffer size
123 if ctrl.addr_mapping.value == 'RoRaBaChCo':
124 # This computation only really needs to happen
125 # once, but as we rely on having an instance we
126 # end up having to repeat it for each and every
127 # one
128 rowbuffer_size = ctrl.device_rowbuffer_size.value * \
129 ctrl.devices_per_rank.value
130
131 intlv_low_bit = int(math.log(rowbuffer_size, 2))
132
133 # We got all we need to configure the appropriate address
134 # range
135 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
136 intlvHighBit = \
137 intlv_low_bit + intlv_bits - 1,
138 xorHighBit = \
139 xor_low_bit + intlv_bits - 1,
140 intlvBits = intlv_bits,
141 intlvMatch = i)
142 return ctrl
143
144def config_mem(options, system):
145 """
146 Create the memory controllers based on the options and attach them.
147
148 If requested, we make a multi-channel configuration of the
149 selected memory controller class by creating multiple instances of
150 the specific class. The individual controllers have their
151 parameters set such that the address range is interleaved between
152 them.
153 """
154
|
| 155 if ( options.mem_type == "HMC_2500_x32"):
156 HMC.config_hmc(options, system)
157 subsystem = system.hmc
158 xbar = system.hmc.xbar
159 else:
160 subsystem = system
161 xbar = system.membus
162
|
154 if options.tlm_memory:
155 system.external_memory = m5.objects.ExternalSlave(
156 port_type="tlm",
157 port_data=options.tlm_memory,
158 port=system.membus.master,
159 addr_ranges=system.mem_ranges)
160 system.kernel_addr_check = False
161 return
162
163 if options.external_memory_system:
| 163 if options.tlm_memory:
164 system.external_memory = m5.objects.ExternalSlave(
165 port_type="tlm",
166 port_data=options.tlm_memory,
167 port=system.membus.master,
168 addr_ranges=system.mem_ranges)
169 system.kernel_addr_check = False
170 return
171
172 if options.external_memory_system:
|
164 system.external_memory = m5.objects.ExternalSlave(
| 173 subsystem.external_memory = m5.objects.ExternalSlave(
|
165 port_type=options.external_memory_system,
| 174 port_type=options.external_memory_system,
|
166 port_data="init_mem0", port=system.membus.master,
| 175 port_data="init_mem0", port=xbar.master,
|
167 addr_ranges=system.mem_ranges)
| 176 addr_ranges=system.mem_ranges)
|
168 system.kernel_addr_check = False
| 177 subsystem.kernel_addr_check = False
|
169 return
170
171 nbr_mem_ctrls = options.mem_channels
172 import math
173 from m5.util import fatal
174 intlv_bits = int(math.log(nbr_mem_ctrls, 2))
175 if 2 ** intlv_bits != nbr_mem_ctrls:
176 fatal("Number of memory channels must be a power of 2")
177
178 cls = get(options.mem_type)
179 mem_ctrls = []
180
181 # The default behaviour is to interleave memory channels on 128
182 # byte granularity, or cache line granularity if larger than 128
183 # byte. This value is based on the locality seen across a large
184 # range of workloads.
185 intlv_size = max(128, system.cache_line_size.value)
186
187 # For every range (most systems will only have one), create an
188 # array of controllers and set their parameters to match their
189 # address mapping in the case of a DRAM
190 for r in system.mem_ranges:
191 for i in xrange(nbr_mem_ctrls):
192 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
193 intlv_size)
194 # Set the number of ranks based on the command-line
195 # options if it was explicitly set
196 if issubclass(cls, m5.objects.DRAMCtrl) and \
197 options.mem_ranks:
198 mem_ctrl.ranks_per_channel = options.mem_ranks
199
200 mem_ctrls.append(mem_ctrl)
201
| 178 return
179
180 nbr_mem_ctrls = options.mem_channels
181 import math
182 from m5.util import fatal
183 intlv_bits = int(math.log(nbr_mem_ctrls, 2))
184 if 2 ** intlv_bits != nbr_mem_ctrls:
185 fatal("Number of memory channels must be a power of 2")
186
187 cls = get(options.mem_type)
188 mem_ctrls = []
189
190 # The default behaviour is to interleave memory channels on 128
191 # byte granularity, or cache line granularity if larger than 128
192 # byte. This value is based on the locality seen across a large
193 # range of workloads.
194 intlv_size = max(128, system.cache_line_size.value)
195
196 # For every range (most systems will only have one), create an
197 # array of controllers and set their parameters to match their
198 # address mapping in the case of a DRAM
199 for r in system.mem_ranges:
200 for i in xrange(nbr_mem_ctrls):
201 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
202 intlv_size)
203 # Set the number of ranks based on the command-line
204 # options if it was explicitly set
205 if issubclass(cls, m5.objects.DRAMCtrl) and \
206 options.mem_ranks:
207 mem_ctrl.ranks_per_channel = options.mem_ranks
208
209 mem_ctrls.append(mem_ctrl)
210
|
202 system.mem_ctrls = mem_ctrls
| 211 subsystem.mem_ctrls = mem_ctrls
|
203
204 # Connect the controllers to the membus
| 212
213 # Connect the controllers to the membus
|
205 for i in xrange(len(system.mem_ctrls)):
206 system.mem_ctrls[i].port = system.membus.master
| 214 for i in xrange(len(subsystem.mem_ctrls)):
215 subsystem.mem_ctrls[i].port = xbar.master
|
| |