1# Copyright (c) 2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42from textwrap import TextWrapper
43
44# Dictionary of mapping names of real memory controller models to
45# classes.
46_mem_classes = {}
47
48# Memory aliases. We make sure they exist before we add them to the
49# fina; list. A target may be specified as a tuple, in which case the
50# first available memory controller model in the tuple will be used.
51_mem_aliases_all = [
52 ("simple_mem", "SimpleMemory"),
53 ("ddr3_1600_x64", "DDR3_1600_x64"),
54 ("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"),
55 ("lpddr3_1600_x32", "LPDDR3_1600_x32"),
56 ("wio_200_x128", "WideIO_200_x128"),
57 ("dramsim2", "DRAMSim2"),
58 ("ruby_memory", "RubyMemoryControl")
59 ]
60
61# Filtered list of aliases. Only aliases for existing memory
62# controllers exist in this list.
63_mem_aliases = {}
64
65
66def is_mem_class(cls):
67 """Determine if a class is a memory controller that can be instantiated"""
68
69 # We can't use the normal inspect.isclass because the ParamFactory
70 # and ProxyFactory classes have a tendency to confuse it.
71 try:
72 return issubclass(cls, m5.objects.AbstractMemory) and \
73 not cls.abstract
74 except TypeError:
75 return False
76
77def get(name):
78 """Get a memory class from a user provided class name or alias."""
79
80 real_name = _mem_aliases.get(name, name)
81
82 try:
83 mem_class = _mem_classes[real_name]
84 return mem_class
85 except KeyError:
86 print "%s is not a valid memory controller." % (name,)
87 sys.exit(1)
88
89def print_mem_list():
90 """Print a list of available memory classes including their aliases."""
91
92 print "Available memory classes:"
93 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
94 for name, cls in _mem_classes.items():
95 print "\t%s" % name
96
97 # Try to extract the class documentation from the class help
98 # string.
99 doc = inspect.getdoc(cls)
100 if doc:
101 for line in doc_wrapper.wrap(doc):
102 print line
103
104 if _mem_aliases:
105 print "\nMemory aliases:"
106 for alias, target in _mem_aliases.items():
107 print "\t%s => %s" % (alias, target)
108
109def mem_names():
110 """Return a list of valid memory names."""
111 return _mem_classes.keys() + _mem_aliases.keys()
112
113# Add all memory controllers in the object hierarchy.
114for name, cls in inspect.getmembers(m5.objects, is_mem_class):
115 _mem_classes[name] = cls
116
117for alias, target in _mem_aliases_all:
118 if isinstance(target, tuple):
119 # Some aliases contain a list of memory controller models
120 # sorted in priority order. Use the first target that's
121 # available.
122 for t in target:
123 if t in _mem_classes:
124 _mem_aliases[alias] = t
125 break
126 elif target in _mem_classes:
127 # Normal alias
128 _mem_aliases[alias] = target
129
130def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
131 """
132 Helper function for creating a single memoy controller from the given
133 options. This function is invoked multiple times in config_mem function
134 to create an array of controllers.
135 """
136
137 import math
138 intlv_low_bit = int(math.log(intlv_size, 2))
139
140 # Use basic hashing for the channel selection, and preferably use
141 # the lower tag bits from the last level cache. As we do not know
142 # the details of the caches here, make an educated guess. 4 MByte
143 # 4-way associative with 64 byte cache lines is 6 offset bits and
144 # 14 index bits.
145 xor_low_bit = 20
146
147 # Create an instance so we can figure out the address
148 # mapping and row-buffer size
149 ctrl = cls()
150
151 # Only do this for DRAMs
152 if issubclass(cls, m5.objects.DRAMCtrl):
153 # Inform each controller how many channels to account
154 # for
155 ctrl.channels = nbr_mem_ctrls
156
157 # If the channel bits are appearing after the column
158 # bits, we need to add the appropriate number of bits
159 # for the row buffer size
160 if ctrl.addr_mapping.value == 'RoRaBaChCo':
161 # This computation only really needs to happen
162 # once, but as we rely on having an instance we
163 # end up having to repeat it for each and every
164 # one
165 rowbuffer_size = ctrl.device_rowbuffer_size.value * \
166 ctrl.devices_per_rank.value
167
168 intlv_low_bit = int(math.log(rowbuffer_size, 2))
169
170 # We got all we need to configure the appropriate address
171 # range
172 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
173 intlvHighBit = \
174 intlv_low_bit + intlv_bits - 1,
175 xorHighBit = \
176 xor_low_bit + intlv_bits - 1,
177 intlvBits = intlv_bits,
178 intlvMatch = i)
179 return ctrl
180
181def config_mem(options, system):
182 """
183 Create the memory controllers based on the options and attach them.
184
185 If requested, we make a multi-channel configuration of the
186 selected memory controller class by creating multiple instances of
187 the specific class. The individual controllers have their
188 parameters set such that the address range is interleaved between
189 them.
190 """
191
| 1# Copyright (c) 2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42from textwrap import TextWrapper
43
44# Dictionary of mapping names of real memory controller models to
45# classes.
46_mem_classes = {}
47
48# Memory aliases. We make sure they exist before we add them to the
49# fina; list. A target may be specified as a tuple, in which case the
50# first available memory controller model in the tuple will be used.
51_mem_aliases_all = [
52 ("simple_mem", "SimpleMemory"),
53 ("ddr3_1600_x64", "DDR3_1600_x64"),
54 ("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"),
55 ("lpddr3_1600_x32", "LPDDR3_1600_x32"),
56 ("wio_200_x128", "WideIO_200_x128"),
57 ("dramsim2", "DRAMSim2"),
58 ("ruby_memory", "RubyMemoryControl")
59 ]
60
61# Filtered list of aliases. Only aliases for existing memory
62# controllers exist in this list.
63_mem_aliases = {}
64
65
66def is_mem_class(cls):
67 """Determine if a class is a memory controller that can be instantiated"""
68
69 # We can't use the normal inspect.isclass because the ParamFactory
70 # and ProxyFactory classes have a tendency to confuse it.
71 try:
72 return issubclass(cls, m5.objects.AbstractMemory) and \
73 not cls.abstract
74 except TypeError:
75 return False
76
77def get(name):
78 """Get a memory class from a user provided class name or alias."""
79
80 real_name = _mem_aliases.get(name, name)
81
82 try:
83 mem_class = _mem_classes[real_name]
84 return mem_class
85 except KeyError:
86 print "%s is not a valid memory controller." % (name,)
87 sys.exit(1)
88
89def print_mem_list():
90 """Print a list of available memory classes including their aliases."""
91
92 print "Available memory classes:"
93 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
94 for name, cls in _mem_classes.items():
95 print "\t%s" % name
96
97 # Try to extract the class documentation from the class help
98 # string.
99 doc = inspect.getdoc(cls)
100 if doc:
101 for line in doc_wrapper.wrap(doc):
102 print line
103
104 if _mem_aliases:
105 print "\nMemory aliases:"
106 for alias, target in _mem_aliases.items():
107 print "\t%s => %s" % (alias, target)
108
109def mem_names():
110 """Return a list of valid memory names."""
111 return _mem_classes.keys() + _mem_aliases.keys()
112
113# Add all memory controllers in the object hierarchy.
114for name, cls in inspect.getmembers(m5.objects, is_mem_class):
115 _mem_classes[name] = cls
116
117for alias, target in _mem_aliases_all:
118 if isinstance(target, tuple):
119 # Some aliases contain a list of memory controller models
120 # sorted in priority order. Use the first target that's
121 # available.
122 for t in target:
123 if t in _mem_classes:
124 _mem_aliases[alias] = t
125 break
126 elif target in _mem_classes:
127 # Normal alias
128 _mem_aliases[alias] = target
129
130def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
131 """
132 Helper function for creating a single memoy controller from the given
133 options. This function is invoked multiple times in config_mem function
134 to create an array of controllers.
135 """
136
137 import math
138 intlv_low_bit = int(math.log(intlv_size, 2))
139
140 # Use basic hashing for the channel selection, and preferably use
141 # the lower tag bits from the last level cache. As we do not know
142 # the details of the caches here, make an educated guess. 4 MByte
143 # 4-way associative with 64 byte cache lines is 6 offset bits and
144 # 14 index bits.
145 xor_low_bit = 20
146
147 # Create an instance so we can figure out the address
148 # mapping and row-buffer size
149 ctrl = cls()
150
151 # Only do this for DRAMs
152 if issubclass(cls, m5.objects.DRAMCtrl):
153 # Inform each controller how many channels to account
154 # for
155 ctrl.channels = nbr_mem_ctrls
156
157 # If the channel bits are appearing after the column
158 # bits, we need to add the appropriate number of bits
159 # for the row buffer size
160 if ctrl.addr_mapping.value == 'RoRaBaChCo':
161 # This computation only really needs to happen
162 # once, but as we rely on having an instance we
163 # end up having to repeat it for each and every
164 # one
165 rowbuffer_size = ctrl.device_rowbuffer_size.value * \
166 ctrl.devices_per_rank.value
167
168 intlv_low_bit = int(math.log(rowbuffer_size, 2))
169
170 # We got all we need to configure the appropriate address
171 # range
172 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
173 intlvHighBit = \
174 intlv_low_bit + intlv_bits - 1,
175 xorHighBit = \
176 xor_low_bit + intlv_bits - 1,
177 intlvBits = intlv_bits,
178 intlvMatch = i)
179 return ctrl
180
181def config_mem(options, system):
182 """
183 Create the memory controllers based on the options and attach them.
184
185 If requested, we make a multi-channel configuration of the
186 selected memory controller class by creating multiple instances of
187 the specific class. The individual controllers have their
188 parameters set such that the address range is interleaved between
189 them.
190 """
191
|
192 nbr_mem_ctrls = options.mem_channels
193 import math
194 from m5.util import fatal
195 intlv_bits = int(math.log(nbr_mem_ctrls, 2))
196 if 2 ** intlv_bits != nbr_mem_ctrls:
197 fatal("Number of memory channels must be a power of 2")
198
199 cls = get(options.mem_type)
200 mem_ctrls = []
201
202 # The default behaviour is to interleave memory channels on 128
203 # byte granularity, or cache line granularity if larger than 128
204 # byte. This value is based on the locality seen across a large
205 # range of workloads.
206 intlv_size = max(128, system.cache_line_size.value)
207
208 # For every range (most systems will only have one), create an
209 # array of controllers and set their parameters to match their
210 # address mapping in the case of a DRAM
211 for r in system.mem_ranges:
212 for i in xrange(nbr_mem_ctrls):
213 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
214 intlv_size)
215 # Set the number of ranks based on the command-line
216 # options if it was explicitly set
217 if issubclass(cls, m5.objects.DRAMCtrl) and \
218 options.mem_ranks:
219 mem_ctrl.ranks_per_channel = options.mem_ranks
220
221 mem_ctrls.append(mem_ctrl)
222
223 system.mem_ctrls = mem_ctrls
224
225 # Connect the controllers to the membus
226 for i in xrange(len(system.mem_ctrls)):
227 system.mem_ctrls[i].port = system.membus.master
| 200 nbr_mem_ctrls = options.mem_channels
201 import math
202 from m5.util import fatal
203 intlv_bits = int(math.log(nbr_mem_ctrls, 2))
204 if 2 ** intlv_bits != nbr_mem_ctrls:
205 fatal("Number of memory channels must be a power of 2")
206
207 cls = get(options.mem_type)
208 mem_ctrls = []
209
210 # The default behaviour is to interleave memory channels on 128
211 # byte granularity, or cache line granularity if larger than 128
212 # byte. This value is based on the locality seen across a large
213 # range of workloads.
214 intlv_size = max(128, system.cache_line_size.value)
215
216 # For every range (most systems will only have one), create an
217 # array of controllers and set their parameters to match their
218 # address mapping in the case of a DRAM
219 for r in system.mem_ranges:
220 for i in xrange(nbr_mem_ctrls):
221 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
222 intlv_size)
223 # Set the number of ranks based on the command-line
224 # options if it was explicitly set
225 if issubclass(cls, m5.objects.DRAMCtrl) and \
226 options.mem_ranks:
227 mem_ctrl.ranks_per_channel = options.mem_ranks
228
229 mem_ctrls.append(mem_ctrl)
230
231 system.mem_ctrls = mem_ctrls
232
233 # Connect the controllers to the membus
234 for i in xrange(len(system.mem_ctrls)):
235 system.mem_ctrls[i].port = system.membus.master
|