1# Copyright (c) 2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42from textwrap import TextWrapper
43
44# Dictionary of mapping names of real memory controller models to
45# classes.
46_mem_classes = {}
47
48# Memory aliases. We make sure they exist before we add them to the
49# fina; list. A target may be specified as a tuple, in which case the
50# first available memory controller model in the tuple will be used.
51_mem_aliases_all = [
52 ("simple_mem", "SimpleMemory"),
53 ("ddr3_1600_x64", "DDR3_1600_x64"),
54 ("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"),
55 ("lpddr3_1600_x32", "LPDDR3_1600_x32"),
56 ("wio_200_x128", "WideIO_200_x128"),
| 1# Copyright (c) 2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42from textwrap import TextWrapper
43
44# Dictionary of mapping names of real memory controller models to
45# classes.
46_mem_classes = {}
47
48# Memory aliases. We make sure they exist before we add them to the
49# fina; list. A target may be specified as a tuple, in which case the
50# first available memory controller model in the tuple will be used.
51_mem_aliases_all = [
52 ("simple_mem", "SimpleMemory"),
53 ("ddr3_1600_x64", "DDR3_1600_x64"),
54 ("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"),
55 ("lpddr3_1600_x32", "LPDDR3_1600_x32"),
56 ("wio_200_x128", "WideIO_200_x128"),
|
57 ("dramsim2", "DRAMSim2")
| 57 ("dramsim2", "DRAMSim2"),
58 ("ruby_memory", "RubyMemoryControl")
|
58 ]
59
60# Filtered list of aliases. Only aliases for existing memory
61# controllers exist in this list.
62_mem_aliases = {}
63
64
65def is_mem_class(cls):
66 """Determine if a class is a memory controller that can be instantiated"""
67
68 # We can't use the normal inspect.isclass because the ParamFactory
69 # and ProxyFactory classes have a tendency to confuse it.
70 try:
71 return issubclass(cls, m5.objects.AbstractMemory) and \
72 not cls.abstract
73 except TypeError:
74 return False
75
76def get(name):
77 """Get a memory class from a user provided class name or alias."""
78
79 real_name = _mem_aliases.get(name, name)
80
81 try:
82 mem_class = _mem_classes[real_name]
83 return mem_class
84 except KeyError:
85 print "%s is not a valid memory controller." % (name,)
86 sys.exit(1)
87
88def print_mem_list():
89 """Print a list of available memory classes including their aliases."""
90
91 print "Available memory classes:"
92 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
93 for name, cls in _mem_classes.items():
94 print "\t%s" % name
95
96 # Try to extract the class documentation from the class help
97 # string.
98 doc = inspect.getdoc(cls)
99 if doc:
100 for line in doc_wrapper.wrap(doc):
101 print line
102
103 if _mem_aliases:
104 print "\nMemory aliases:"
105 for alias, target in _mem_aliases.items():
106 print "\t%s => %s" % (alias, target)
107
108def mem_names():
109 """Return a list of valid memory names."""
110 return _mem_classes.keys() + _mem_aliases.keys()
111
112# Add all memory controllers in the object hierarchy.
113for name, cls in inspect.getmembers(m5.objects, is_mem_class):
114 _mem_classes[name] = cls
115
116for alias, target in _mem_aliases_all:
117 if isinstance(target, tuple):
118 # Some aliases contain a list of memory controller models
119 # sorted in priority order. Use the first target that's
120 # available.
121 for t in target:
122 if t in _mem_classes:
123 _mem_aliases[alias] = t
124 break
125 elif target in _mem_classes:
126 # Normal alias
127 _mem_aliases[alias] = target
128
129def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, cache_line_size):
130 """
131 Helper function for creating a single memoy controller from the given
132 options. This function is invoked multiple times in config_mem function
133 to create an array of controllers.
134 """
135
136 import math
137 # The default behaviour is to interleave on cache line granularity
138 cache_line_bit = int(math.log(cache_line_size, 2)) - 1
139 intlv_low_bit = cache_line_bit
140
141 # Create an instance so we can figure out the address
142 # mapping and row-buffer size
143 ctrl = cls()
144
145 # Only do this for DRAMs
146 if issubclass(cls, m5.objects.DRAMCtrl):
147 # Inform each controller how many channels to account
148 # for
149 ctrl.channels = nbr_mem_ctrls
150
151 # If the channel bits are appearing after the column
152 # bits, we need to add the appropriate number of bits
153 # for the row buffer size
154 if ctrl.addr_mapping.value == 'RoRaBaChCo':
155 # This computation only really needs to happen
156 # once, but as we rely on having an instance we
157 # end up having to repeat it for each and every
158 # one
159 rowbuffer_size = ctrl.device_rowbuffer_size.value * \
160 ctrl.devices_per_rank.value
161
162 intlv_low_bit = int(math.log(rowbuffer_size, 2)) - 1
163
164 # We got all we need to configure the appropriate address
165 # range
166 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
167 intlvHighBit = \
168 intlv_low_bit + intlv_bits,
169 intlvBits = intlv_bits,
170 intlvMatch = i)
171 return ctrl
172
173def config_mem(options, system):
174 """
175 Create the memory controllers based on the options and attach them.
176
177 If requested, we make a multi-channel configuration of the
178 selected memory controller class by creating multiple instances of
179 the specific class. The individual controllers have their
180 parameters set such that the address range is interleaved between
181 them.
182 """
183
184 nbr_mem_ctrls = options.mem_channels
185 import math
186 from m5.util import fatal
187 intlv_bits = int(math.log(nbr_mem_ctrls, 2))
188 if 2 ** intlv_bits != nbr_mem_ctrls:
189 fatal("Number of memory channels must be a power of 2")
190
191 cls = get(options.mem_type)
192 mem_ctrls = []
193
194 # For every range (most systems will only have one), create an
195 # array of controllers and set their parameters to match their
196 # address mapping in the case of a DRAM
197 for r in system.mem_ranges:
198 for i in xrange(nbr_mem_ctrls):
199 mem_ctrls.append(create_mem_ctrl(cls, r, i, nbr_mem_ctrls,
200 intlv_bits,
201 system.cache_line_size.value))
202
203 system.mem_ctrls = mem_ctrls
204
205 # Connect the controllers to the membus
206 for i in xrange(len(system.mem_ctrls)):
207 system.mem_ctrls[i].port = system.membus.master
| 59 ]
60
61# Filtered list of aliases. Only aliases for existing memory
62# controllers exist in this list.
63_mem_aliases = {}
64
65
66def is_mem_class(cls):
67 """Determine if a class is a memory controller that can be instantiated"""
68
69 # We can't use the normal inspect.isclass because the ParamFactory
70 # and ProxyFactory classes have a tendency to confuse it.
71 try:
72 return issubclass(cls, m5.objects.AbstractMemory) and \
73 not cls.abstract
74 except TypeError:
75 return False
76
77def get(name):
78 """Get a memory class from a user provided class name or alias."""
79
80 real_name = _mem_aliases.get(name, name)
81
82 try:
83 mem_class = _mem_classes[real_name]
84 return mem_class
85 except KeyError:
86 print "%s is not a valid memory controller." % (name,)
87 sys.exit(1)
88
89def print_mem_list():
90 """Print a list of available memory classes including their aliases."""
91
92 print "Available memory classes:"
93 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
94 for name, cls in _mem_classes.items():
95 print "\t%s" % name
96
97 # Try to extract the class documentation from the class help
98 # string.
99 doc = inspect.getdoc(cls)
100 if doc:
101 for line in doc_wrapper.wrap(doc):
102 print line
103
104 if _mem_aliases:
105 print "\nMemory aliases:"
106 for alias, target in _mem_aliases.items():
107 print "\t%s => %s" % (alias, target)
108
109def mem_names():
110 """Return a list of valid memory names."""
111 return _mem_classes.keys() + _mem_aliases.keys()
112
113# Add all memory controllers in the object hierarchy.
114for name, cls in inspect.getmembers(m5.objects, is_mem_class):
115 _mem_classes[name] = cls
116
117for alias, target in _mem_aliases_all:
118 if isinstance(target, tuple):
119 # Some aliases contain a list of memory controller models
120 # sorted in priority order. Use the first target that's
121 # available.
122 for t in target:
123 if t in _mem_classes:
124 _mem_aliases[alias] = t
125 break
126 elif target in _mem_classes:
127 # Normal alias
128 _mem_aliases[alias] = target
129
130def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, cache_line_size):
131 """
132 Helper function for creating a single memoy controller from the given
133 options. This function is invoked multiple times in config_mem function
134 to create an array of controllers.
135 """
136
137 import math
138 # The default behaviour is to interleave on cache line granularity
139 cache_line_bit = int(math.log(cache_line_size, 2)) - 1
140 intlv_low_bit = cache_line_bit
141
142 # Create an instance so we can figure out the address
143 # mapping and row-buffer size
144 ctrl = cls()
145
146 # Only do this for DRAMs
147 if issubclass(cls, m5.objects.DRAMCtrl):
148 # Inform each controller how many channels to account
149 # for
150 ctrl.channels = nbr_mem_ctrls
151
152 # If the channel bits are appearing after the column
153 # bits, we need to add the appropriate number of bits
154 # for the row buffer size
155 if ctrl.addr_mapping.value == 'RoRaBaChCo':
156 # This computation only really needs to happen
157 # once, but as we rely on having an instance we
158 # end up having to repeat it for each and every
159 # one
160 rowbuffer_size = ctrl.device_rowbuffer_size.value * \
161 ctrl.devices_per_rank.value
162
163 intlv_low_bit = int(math.log(rowbuffer_size, 2)) - 1
164
165 # We got all we need to configure the appropriate address
166 # range
167 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
168 intlvHighBit = \
169 intlv_low_bit + intlv_bits,
170 intlvBits = intlv_bits,
171 intlvMatch = i)
172 return ctrl
173
174def config_mem(options, system):
175 """
176 Create the memory controllers based on the options and attach them.
177
178 If requested, we make a multi-channel configuration of the
179 selected memory controller class by creating multiple instances of
180 the specific class. The individual controllers have their
181 parameters set such that the address range is interleaved between
182 them.
183 """
184
185 nbr_mem_ctrls = options.mem_channels
186 import math
187 from m5.util import fatal
188 intlv_bits = int(math.log(nbr_mem_ctrls, 2))
189 if 2 ** intlv_bits != nbr_mem_ctrls:
190 fatal("Number of memory channels must be a power of 2")
191
192 cls = get(options.mem_type)
193 mem_ctrls = []
194
195 # For every range (most systems will only have one), create an
196 # array of controllers and set their parameters to match their
197 # address mapping in the case of a DRAM
198 for r in system.mem_ranges:
199 for i in xrange(nbr_mem_ctrls):
200 mem_ctrls.append(create_mem_ctrl(cls, r, i, nbr_mem_ctrls,
201 intlv_bits,
202 system.cache_line_size.value))
203
204 system.mem_ctrls = mem_ctrls
205
206 # Connect the controllers to the membus
207 for i in xrange(len(system.mem_ctrls)):
208 system.mem_ctrls[i].port = system.membus.master
|