1# Copyright (c) 2013, 2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42import HMC
43from textwrap import TextWrapper
44
45# Dictionary of mapping names of real memory controller models to
46# classes.
47_mem_classes = {}
48
49def is_mem_class(cls):
50 """Determine if a class is a memory controller that can be instantiated"""
51
52 # We can't use the normal inspect.isclass because the ParamFactory
53 # and ProxyFactory classes have a tendency to confuse it.
54 try:
55 return issubclass(cls, m5.objects.AbstractMemory) and \
56 not cls.abstract
57 except TypeError:
58 return False
59
60def get(name):
61 """Get a memory class from a user provided class name."""
62
63 try:
64 mem_class = _mem_classes[name]
65 return mem_class
66 except KeyError:
67 print "%s is not a valid memory controller." % (name,)
68 sys.exit(1)
69
70def print_mem_list():
71 """Print a list of available memory classes."""
72
73 print "Available memory classes:"
74 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
75 for name, cls in _mem_classes.items():
76 print "\t%s" % name
77
78 # Try to extract the class documentation from the class help
79 # string.
80 doc = inspect.getdoc(cls)
81 if doc:
82 for line in doc_wrapper.wrap(doc):
83 print line
84
85def mem_names():
86 """Return a list of valid memory names."""
87 return _mem_classes.keys()
88
89# Add all memory controllers in the object hierarchy.
90for name, cls in inspect.getmembers(m5.objects, is_mem_class):
91 _mem_classes[name] = cls
92
93def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
94 """
95 Helper function for creating a single memoy controller from the given
96 options. This function is invoked multiple times in config_mem function
97 to create an array of controllers.
98 """
99
100 import math
101 intlv_low_bit = int(math.log(intlv_size, 2))
102
103 # Use basic hashing for the channel selection, and preferably use
104 # the lower tag bits from the last level cache. As we do not know
105 # the details of the caches here, make an educated guess. 4 MByte
106 # 4-way associative with 64 byte cache lines is 6 offset bits and
107 # 14 index bits.
108 xor_low_bit = 20
109
110 # Create an instance so we can figure out the address
111 # mapping and row-buffer size
112 ctrl = cls()
113
114 # Only do this for DRAMs
115 if issubclass(cls, m5.objects.DRAMCtrl):
116 # Inform each controller how many channels to account
117 # for
118 ctrl.channels = nbr_mem_ctrls
119
120 # If the channel bits are appearing after the column
121 # bits, we need to add the appropriate number of bits
122 # for the row buffer size
123 if ctrl.addr_mapping.value == 'RoRaBaChCo':
124 # This computation only really needs to happen
125 # once, but as we rely on having an instance we
126 # end up having to repeat it for each and every
127 # one
128 rowbuffer_size = ctrl.device_rowbuffer_size.value * \
129 ctrl.devices_per_rank.value
130
131 intlv_low_bit = int(math.log(rowbuffer_size, 2))
132
133 # We got all we need to configure the appropriate address
134 # range
135 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
136 intlvHighBit = \
137 intlv_low_bit + intlv_bits - 1,
138 xorHighBit = \
139 xor_low_bit + intlv_bits - 1,
140 intlvBits = intlv_bits,
141 intlvMatch = i)
142 return ctrl
143
144def config_mem(options, system):
145 """
146 Create the memory controllers based on the options and attach them.
147
148 If requested, we make a multi-channel configuration of the
149 selected memory controller class by creating multiple instances of
150 the specific class. The individual controllers have their
151 parameters set such that the address range is interleaved between
152 them.
153 """
154
155 # Mandatory options
156 opt_mem_type = options.mem_type
157 opt_mem_channels = options.mem_channels
158
159 # Optional options
160 opt_tlm_memory = getattr(options, "tlm_memory", None)
161 opt_external_memory_system = getattr(options, "external_memory_system",
162 None)
163 opt_elastic_trace_en = getattr(options, "elastic_trace_en", False)
164 opt_mem_ranks = getattr(options, "mem_ranks", None)
165
166 if opt_mem_type == "HMC_2500_1x32":
167 HMChost = HMC.config_hmc_host_ctrl(options, system)
168 HMC.config_hmc_dev(options, system, HMChost.hmc_host)
169 subsystem = system.hmc_dev
170 xbar = system.hmc_dev.xbar
171 else:
172 subsystem = system
173 xbar = system.membus
174
175 if opt_tlm_memory:
176 system.external_memory = m5.objects.ExternalSlave(
177 port_type="tlm_slave",
178 port_data=opt_tlm_memory,
179 port=system.membus.master,
180 addr_ranges=system.mem_ranges)
181 system.kernel_addr_check = False
182 return
183
184 if opt_external_memory_system:
185 subsystem.external_memory = m5.objects.ExternalSlave(
186 port_type=opt_external_memory_system,
187 port_data="init_mem0", port=xbar.master,
188 addr_ranges=system.mem_ranges)
189 subsystem.kernel_addr_check = False
190 return
191
192 nbr_mem_ctrls = opt_mem_channels
193 import math
194 from m5.util import fatal
195 intlv_bits = int(math.log(nbr_mem_ctrls, 2))
196 if 2 ** intlv_bits != nbr_mem_ctrls:
197 fatal("Number of memory channels must be a power of 2")
198
199 cls = get(opt_mem_type)
200 mem_ctrls = []
201
202 if opt_elastic_trace_en and not issubclass(cls, m5.objects.SimpleMemory):
203 fatal("When elastic trace is enabled, configure mem-type as "
204 "simple-mem.")
205
206 # The default behaviour is to interleave memory channels on 128
207 # byte granularity, or cache line granularity if larger than 128
208 # byte. This value is based on the locality seen across a large
209 # range of workloads.
210 intlv_size = max(128, system.cache_line_size.value)
211
212 # For every range (most systems will only have one), create an
213 # array of controllers and set their parameters to match their
214 # address mapping in the case of a DRAM
215 for r in system.mem_ranges:
216 for i in xrange(nbr_mem_ctrls):
217 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
218 intlv_size)
219 # Set the number of ranks based on the command-line
220 # options if it was explicitly set
221 if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
222 mem_ctrl.ranks_per_channel = opt_mem_ranks
223
224 if opt_elastic_trace_en:
225 mem_ctrl.latency = '1ns'
226 print "For elastic trace, over-riding Simple Memory " \
227 "latency to 1ns."
228
229 mem_ctrls.append(mem_ctrl)
230
231 subsystem.mem_ctrls = mem_ctrls
232
233 # Connect the controllers to the membus
234 for i in xrange(len(subsystem.mem_ctrls)):
235 if opt_mem_type == "HMC_2500_1x32":
236 subsystem.mem_ctrls[i].port = xbar[i/4].master
237 # Set memory device size. There is an independent controller for
238 # each vault. All vaults are same size.
239 subsystem.mem_ctrls[i].device_size = options.hmc_dev_vault_size
240 else:
241 subsystem.mem_ctrls[i].port = xbar.master
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42import HMC
43from textwrap import TextWrapper
44
45# Dictionary of mapping names of real memory controller models to
46# classes.
47_mem_classes = {}
48
49def is_mem_class(cls):
50 """Determine if a class is a memory controller that can be instantiated"""
51
52 # We can't use the normal inspect.isclass because the ParamFactory
53 # and ProxyFactory classes have a tendency to confuse it.
54 try:
55 return issubclass(cls, m5.objects.AbstractMemory) and \
56 not cls.abstract
57 except TypeError:
58 return False
59
60def get(name):
61 """Get a memory class from a user provided class name."""
62
63 try:
64 mem_class = _mem_classes[name]
65 return mem_class
66 except KeyError:
67 print "%s is not a valid memory controller." % (name,)
68 sys.exit(1)
69
70def print_mem_list():
71 """Print a list of available memory classes."""
72
73 print "Available memory classes:"
74 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
75 for name, cls in _mem_classes.items():
76 print "\t%s" % name
77
78 # Try to extract the class documentation from the class help
79 # string.
80 doc = inspect.getdoc(cls)
81 if doc:
82 for line in doc_wrapper.wrap(doc):
83 print line
84
85def mem_names():
86 """Return a list of valid memory names."""
87 return _mem_classes.keys()
88
89# Add all memory controllers in the object hierarchy.
90for name, cls in inspect.getmembers(m5.objects, is_mem_class):
91 _mem_classes[name] = cls
92
93def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
94 """
95 Helper function for creating a single memoy controller from the given
96 options. This function is invoked multiple times in config_mem function
97 to create an array of controllers.
98 """
99
100 import math
101 intlv_low_bit = int(math.log(intlv_size, 2))
102
103 # Use basic hashing for the channel selection, and preferably use
104 # the lower tag bits from the last level cache. As we do not know
105 # the details of the caches here, make an educated guess. 4 MByte
106 # 4-way associative with 64 byte cache lines is 6 offset bits and
107 # 14 index bits.
108 xor_low_bit = 20
109
110 # Create an instance so we can figure out the address
111 # mapping and row-buffer size
112 ctrl = cls()
113
114 # Only do this for DRAMs
115 if issubclass(cls, m5.objects.DRAMCtrl):
116 # Inform each controller how many channels to account
117 # for
118 ctrl.channels = nbr_mem_ctrls
119
120 # If the channel bits are appearing after the column
121 # bits, we need to add the appropriate number of bits
122 # for the row buffer size
123 if ctrl.addr_mapping.value == 'RoRaBaChCo':
124 # This computation only really needs to happen
125 # once, but as we rely on having an instance we
126 # end up having to repeat it for each and every
127 # one
128 rowbuffer_size = ctrl.device_rowbuffer_size.value * \
129 ctrl.devices_per_rank.value
130
131 intlv_low_bit = int(math.log(rowbuffer_size, 2))
132
133 # We got all we need to configure the appropriate address
134 # range
135 ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
136 intlvHighBit = \
137 intlv_low_bit + intlv_bits - 1,
138 xorHighBit = \
139 xor_low_bit + intlv_bits - 1,
140 intlvBits = intlv_bits,
141 intlvMatch = i)
142 return ctrl
143
144def config_mem(options, system):
145 """
146 Create the memory controllers based on the options and attach them.
147
148 If requested, we make a multi-channel configuration of the
149 selected memory controller class by creating multiple instances of
150 the specific class. The individual controllers have their
151 parameters set such that the address range is interleaved between
152 them.
153 """
154
155 # Mandatory options
156 opt_mem_type = options.mem_type
157 opt_mem_channels = options.mem_channels
158
159 # Optional options
160 opt_tlm_memory = getattr(options, "tlm_memory", None)
161 opt_external_memory_system = getattr(options, "external_memory_system",
162 None)
163 opt_elastic_trace_en = getattr(options, "elastic_trace_en", False)
164 opt_mem_ranks = getattr(options, "mem_ranks", None)
165
166 if opt_mem_type == "HMC_2500_1x32":
167 HMChost = HMC.config_hmc_host_ctrl(options, system)
168 HMC.config_hmc_dev(options, system, HMChost.hmc_host)
169 subsystem = system.hmc_dev
170 xbar = system.hmc_dev.xbar
171 else:
172 subsystem = system
173 xbar = system.membus
174
175 if opt_tlm_memory:
176 system.external_memory = m5.objects.ExternalSlave(
177 port_type="tlm_slave",
178 port_data=opt_tlm_memory,
179 port=system.membus.master,
180 addr_ranges=system.mem_ranges)
181 system.kernel_addr_check = False
182 return
183
184 if opt_external_memory_system:
185 subsystem.external_memory = m5.objects.ExternalSlave(
186 port_type=opt_external_memory_system,
187 port_data="init_mem0", port=xbar.master,
188 addr_ranges=system.mem_ranges)
189 subsystem.kernel_addr_check = False
190 return
191
192 nbr_mem_ctrls = opt_mem_channels
193 import math
194 from m5.util import fatal
195 intlv_bits = int(math.log(nbr_mem_ctrls, 2))
196 if 2 ** intlv_bits != nbr_mem_ctrls:
197 fatal("Number of memory channels must be a power of 2")
198
199 cls = get(opt_mem_type)
200 mem_ctrls = []
201
202 if opt_elastic_trace_en and not issubclass(cls, m5.objects.SimpleMemory):
203 fatal("When elastic trace is enabled, configure mem-type as "
204 "simple-mem.")
205
206 # The default behaviour is to interleave memory channels on 128
207 # byte granularity, or cache line granularity if larger than 128
208 # byte. This value is based on the locality seen across a large
209 # range of workloads.
210 intlv_size = max(128, system.cache_line_size.value)
211
212 # For every range (most systems will only have one), create an
213 # array of controllers and set their parameters to match their
214 # address mapping in the case of a DRAM
215 for r in system.mem_ranges:
216 for i in xrange(nbr_mem_ctrls):
217 mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
218 intlv_size)
219 # Set the number of ranks based on the command-line
220 # options if it was explicitly set
221 if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
222 mem_ctrl.ranks_per_channel = opt_mem_ranks
223
224 if opt_elastic_trace_en:
225 mem_ctrl.latency = '1ns'
226 print "For elastic trace, over-riding Simple Memory " \
227 "latency to 1ns."
228
229 mem_ctrls.append(mem_ctrl)
230
231 subsystem.mem_ctrls = mem_ctrls
232
233 # Connect the controllers to the membus
234 for i in xrange(len(subsystem.mem_ctrls)):
235 if opt_mem_type == "HMC_2500_1x32":
236 subsystem.mem_ctrls[i].port = xbar[i/4].master
237 # Set memory device size. There is an independent controller for
238 # each vault. All vaults are same size.
239 subsystem.mem_ctrls[i].device_size = options.hmc_dev_vault_size
240 else:
241 subsystem.mem_ctrls[i].port = xbar.master