1# Copyright (c) 2013, 2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42import HMC
43from textwrap import TextWrapper
44
45# Dictionary of mapping names of real memory controller models to
46# classes.

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59
60def get(name):
61 """Get a memory class from a user provided class name."""
62
63 try:
64 mem_class = _mem_classes[name]
65 return mem_class
66 except KeyError:
67 print "%s is not a valid memory controller." % (name,)
68 sys.exit(1)
69
70def print_mem_list():
71 """Print a list of available memory classes."""
72
73 print "Available memory classes:"
74 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
75 for name, cls in _mem_classes.items():
76 print "\t%s" % name
77
78 # Try to extract the class documentation from the class help
79 # string.
80 doc = inspect.getdoc(cls)
81 if doc:
82 for line in doc_wrapper.wrap(doc):
83 print line
84
85def mem_names():
86 """Return a list of valid memory names."""
87 return _mem_classes.keys()
88
89# Add all memory controllers in the object hierarchy.
90for name, cls in inspect.getmembers(m5.objects, is_mem_class):
91 _mem_classes[name] = cls

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218 intlv_size)
219 # Set the number of ranks based on the command-line
220 # options if it was explicitly set
221 if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
222 mem_ctrl.ranks_per_channel = opt_mem_ranks
223
224 if opt_elastic_trace_en:
225 mem_ctrl.latency = '1ns'
226 print "For elastic trace, over-riding Simple Memory " \
227 "latency to 1ns."
228
229 mem_ctrls.append(mem_ctrl)
230
231 subsystem.mem_ctrls = mem_ctrls
232
233 # Connect the controllers to the membus
234 for i in xrange(len(subsystem.mem_ctrls)):
235 if opt_mem_type == "HMC_2500_1x32":
236 subsystem.mem_ctrls[i].port = xbar[i/4].master
237 # Set memory device size. There is an independent controller for
238 # each vault. All vaults are same size.
239 subsystem.mem_ctrls[i].device_size = options.hmc_dev_vault_size
240 else:
241 subsystem.mem_ctrls[i].port = xbar.master