1# Copyright (c) 2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37# Andreas Hansson
38
39import m5.objects
40import inspect
41import sys
42from textwrap import TextWrapper
43
44# Dictionary of mapping names of real memory controller models to
45# classes.
46_mem_classes = {}
47
48def is_mem_class(cls):
49 """Determine if a class is a memory controller that can be instantiated"""

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146
147 If requested, we make a multi-channel configuration of the
148 selected memory controller class by creating multiple instances of
149 the specific class. The individual controllers have their
150 parameters set such that the address range is interleaved between
151 them.
152 """
153
154 if options.tlm_memory:
155 system.external_memory = m5.objects.ExternalSlave(
156 port_type="tlm",
157 port_data=options.tlm_memory,
158 port=system.membus.master,
159 addr_ranges=system.mem_ranges)
160 system.kernel_addr_check = False
161 return
162
163 if options.external_memory_system:
164 system.external_memory = m5.objects.ExternalSlave(
165 port_type=options.external_memory_system,
166 port_data="init_mem0", port=system.membus.master,
167 addr_ranges=system.mem_ranges)
168 system.kernel_addr_check = False
169 return
170
171 nbr_mem_ctrls = options.mem_channels
172 import math
173 from m5.util import fatal
174 intlv_bits = int(math.log(nbr_mem_ctrls, 2))
175 if 2 ** intlv_bits != nbr_mem_ctrls:
176 fatal("Number of memory channels must be a power of 2")

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194 # Set the number of ranks based on the command-line
195 # options if it was explicitly set
196 if issubclass(cls, m5.objects.DRAMCtrl) and \
197 options.mem_ranks:
198 mem_ctrl.ranks_per_channel = options.mem_ranks
199
200 mem_ctrls.append(mem_ctrl)
201
202 system.mem_ctrls = mem_ctrls
203
204 # Connect the controllers to the membus
205 for i in xrange(len(system.mem_ctrls)):
206 system.mem_ctrls[i].port = system.membus.master