HMC.py (11292:5d1d5bf9c178) | HMC.py (11551:d24ad08b22b0) |
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1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 23 unchanged lines hidden (view full) --- 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Erfan Azarkhish | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 23 unchanged lines hidden (view full) --- 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Erfan Azarkhish |
40# Abdul Mutaal Ahmad |
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40 41# A Simplified model of a complete HMC device. Based on: 42# [1] http://www.hybridmemorycube.org/specification-download/ 43# [2] High performance AXI-4.0 based interconnect for extensible smart memory 44# cubes(E. Azarkhish et. al) 45# [3] Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level 46# Prefetching (J. Ahn et. al) 47# [4] Memory-centric system interconnect design with Hybrid Memory Cubes 48# (G. Kim et. al) 49# [5] Near Data Processing, Are we there yet? (M. Gokhale) 50# http://www.cs.utah.edu/wondp/gokhale.pdf | 41 42# A Simplified model of a complete HMC device. Based on: 43# [1] http://www.hybridmemorycube.org/specification-download/ 44# [2] High performance AXI-4.0 based interconnect for extensible smart memory 45# cubes(E. Azarkhish et. al) 46# [3] Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level 47# Prefetching (J. Ahn et. al) 48# [4] Memory-centric system interconnect design with Hybrid Memory Cubes 49# (G. Kim et. al) 50# [5] Near Data Processing, Are we there yet? (M. Gokhale) 51# http://www.cs.utah.edu/wondp/gokhale.pdf |
52# [6] openHMC - A Configurable Open-Source Hybrid Memory Cube Controller 53# (J. Schmidt) 54# [7] Hybrid Memory Cube performance characterization on data-centric 55# workloads (M. Gokhale) |
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51# 52# This script builds a complete HMC device composed of vault controllers, 53# serial links, the main internal crossbar, and an external hmc controller. 54# 55# - VAULT CONTROLLERS: 56# Instances of the HMC_2500_x32 class with their functionality specified in 57# dram_ctrl.cc 58# 59# - THE MAIN XBAR: 60# This component is simply an instance of the NoncoherentXBar class, and its 61# parameters are tuned to [2]. 62# | 56# 57# This script builds a complete HMC device composed of vault controllers, 58# serial links, the main internal crossbar, and an external hmc controller. 59# 60# - VAULT CONTROLLERS: 61# Instances of the HMC_2500_x32 class with their functionality specified in 62# dram_ctrl.cc 63# 64# - THE MAIN XBAR: 65# This component is simply an instance of the NoncoherentXBar class, and its 66# parameters are tuned to [2]. 67# |
63# - SERIAL LINKS: | 68# - SERIAL LINKS CONTROLLER: |
64# SerialLink is a simple variation of the Bridge class, with the ability to | 69# SerialLink is a simple variation of the Bridge class, with the ability to |
65# account for the latency of packet serialization. We assume that the 66# serializer component at the transmitter side does not need to receive the 67# whole packet to start the serialization. But the deserializer waits for 68# the complete packet to check its integrity first. | 70# account for the latency of packet serialization and controller latency. We 71# assume that the serializer component at the transmitter side does not need 72# to receive the whole packet to start the serialization. But the 73# deserializer waits for the complete packet to check its integrity first. 74# |
69# * Bandwidth of the serial links is not modeled in the SerialLink component | 75# * Bandwidth of the serial links is not modeled in the SerialLink component |
70# itself. Instead bandwidth/port of the HMCController has been adjusted to 71# reflect the bandwidth delivered by 1 serial link. | 76# itself. |
72# | 77# |
73# - HMC CONTROLLER: 74# Contains a large buffer (modeled with Bridge) to hide the access latency 75# of the memory cube. Plus it simply forwards the packets to the serial 76# links in a round-robin fashion to balance load among them. | 78# * Latency of serial link controller is composed of SerDes latency + link 79# controller 80# |
77# * It is inferred from the standard [1] and the literature [3] that serial 78# links share the same address range and packets can travel over any of 79# them so a load distribution mechanism is required among them. | 81# * It is inferred from the standard [1] and the literature [3] that serial 82# links share the same address range and packets can travel over any of 83# them so a load distribution mechanism is required among them. |
84# 85# ----------------------------------------- 86# | Host/HMC Controller | 87# | ---------------------- | 88# | | Link Aggregator | opt | 89# | ---------------------- | 90# | ---------------------- | 91# | | Serial Link + Ser | * 4 | 92# | ---------------------- | 93# |--------------------------------------- 94# ----------------------------------------- 95# | Device 96# | ---------------------- | 97# | | Xbar | * 4 | 98# | ---------------------- | 99# | ---------------------- | 100# | | Vault Controller | * 16 | 101# | ---------------------- | 102# | ---------------------- | 103# | | Memory | | 104# | ---------------------- | 105# |---------------------------------------| 106# 107# In this version we have present 3 different HMC archiecture along with 108# alongwith their corresponding test script. 109# 110# same: It has 4 crossbars in HMC memory. All the crossbars are connected 111# to each other, providing complete memory range. This archicture also covers 112# the added latency for sending a request to non-local vault(bridge in b/t 113# crossbars). All the 4 serial links can access complete memory. So each 114# link can be connected to separate processor. 115# 116# distributed: It has 4 crossbars inside the HMC. Crossbars are not 117# connected.Through each crossbar only local vaults can be accessed. But to 118# support this architecture we need a crossbar between serial links and 119# processor. 120# 121# mixed: This is a hybrid architecture. It has 4 crossbars inside the HMC. 122# 2 Crossbars are connected to only local vaults. From other 2 crossbar, a 123# request can be forwarded to any other vault. |
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80 81import optparse 82 83import m5 84from m5.objects import * 85 86# A single Hybrid Memory Cube (HMC) 87class HMCSystem(SubSystem): --- 14 unchanged lines hidden (view full) --- 102 # Latency to forward a packet via the interconnect [1](two levels of FIFOs 103 # at the input and output of the inteconnect) 104 xbar_forward_latency = Param.Cycles(2, "Forward latency of the XBar") 105 106 # Latency to forward a response via the interconnect [1](two levels of 107 # FIFOs at the input and output of the inteconnect) 108 xbar_response_latency = Param.Cycles(2, "Response latency of the XBar") 109 | 124 125import optparse 126 127import m5 128from m5.objects import * 129 130# A single Hybrid Memory Cube (HMC) 131class HMCSystem(SubSystem): --- 14 unchanged lines hidden (view full) --- 146 # Latency to forward a packet via the interconnect [1](two levels of FIFOs 147 # at the input and output of the inteconnect) 148 xbar_forward_latency = Param.Cycles(2, "Forward latency of the XBar") 149 150 # Latency to forward a response via the interconnect [1](two levels of 151 # FIFOs at the input and output of the inteconnect) 152 xbar_response_latency = Param.Cycles(2, "Response latency of the XBar") 153 |
110 #*****************************SERIAL LINK PARAMETERS********************** 111 # Number of serial links [1] 112 num_serial_links = Param.Unsigned(4, "Number of serial links") | 154 # number of cross which connects 16 Vaults to serial link[7] 155 number_mem_crossbar = Param.Unsigned(4, "Number of crossbar in HMC" 156 ) |
113 | 157 |
158 #*****************************SERIAL LINK PARAMETERS*********************** 159 # Number of serial links controllers [1] 160 num_links_controllers = Param.Unsigned(4, "Number of serial links") 161 |
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114 # Number of packets (not flits) to store at the request side of the serial 115 # link. This number should be adjusted to achive required bandwidth | 162 # Number of packets (not flits) to store at the request side of the serial 163 # link. This number should be adjusted to achive required bandwidth |
116 link_buffer_size_req = Param.Unsigned(16, "Number of packets to buffer " | 164 link_buffer_size_req = Param.Unsigned(10, "Number of packets to buffer " |
117 "at the request side of the serial link") 118 119 # Number of packets (not flits) to store at the response side of the serial 120 # link. This number should be adjusted to achive required bandwidth | 165 "at the request side of the serial link") 166 167 # Number of packets (not flits) to store at the response side of the serial 168 # link. This number should be adjusted to achive required bandwidth |
121 link_buffer_size_rsp = Param.Unsigned(16, "Number of packets to buffer " | 169 link_buffer_size_rsp = Param.Unsigned(10, "Number of packets to buffer " |
122 "at the response side of the serial link") 123 124 # Latency of the serial link composed by SER/DES latency (1.6ns [4]) plus 125 # the PCB trace latency (3ns Estimated based on [5]) 126 link_latency = Param.Latency('4.6ns', "Latency of the serial links") 127 | 170 "at the response side of the serial link") 171 172 # Latency of the serial link composed by SER/DES latency (1.6ns [4]) plus 173 # the PCB trace latency (3ns Estimated based on [5]) 174 link_latency = Param.Latency('4.6ns', "Latency of the serial links") 175 |
128 # Header overhead of the serial links: Header size is 128bits in HMC [1], 129 # and we have 16 lanes, so the overhead is 8 cycles 130 link_overhead = Param.Cycles(8, "The number of cycles required to" 131 " transmit the packet header over the serial link") 132 133 # Clock frequency of the serial links [1] | 176 # Clock frequency of the each serial link(SerDes) [1] |
134 link_frequency = Param.Frequency('10GHz', "Clock Frequency of the serial" 135 "links") 136 | 177 link_frequency = Param.Frequency('10GHz', "Clock Frequency of the serial" 178 "links") 179 |
137 # Number of parallel lanes in each serial link [1] 138 num_lanes_per_link = Param.Unsigned(16, "Number of lanes per each link") | 180 # Clock frequency of serial link Controller[6] 181 # clk_hmc[Mhz]= num_lanes_per_link * lane_speed [Gbits/s] / 182 # data_path_width * 10^6 183 # clk_hmc[Mhz]= 16 * 10 Gbps / 256 * 10^6 = 625 Mhz 184 link_controller_frequency = Param.Frequency('625MHz', 185 "Clock Frequency of the link controller") |
139 | 186 |
140 # Number of serial links [1] 141 num_serial_links = Param.Unsigned(4, "Number of serial links") | 187 # Latency of the serial link controller to process the packets[1][6] 188 # (ClockDomain = 625 Mhz ) 189 # used here for calculations only 190 link_ctrl_latency = Param.Cycles(4, "The number of cycles required for the" 191 "controller to process the packet") |
142 | 192 |
143 #*****************************HMC CONTROLLER PARAMETERS******************* 144 # Number of packets (not flits) to store at the HMC controller. This 145 # number should be high enough to be able to hide the high latency of HMC 146 ctrl_buffer_size_req = Param.Unsigned(256, "Number of packets to buffer " 147 "at the HMC controller (request side)") | 193 # total_ctrl_latency = link_ctrl_latency + link_latency 194 # total_ctrl_latency = 4(Cycles) * 1.6 ns + 4.6 ns 195 total_ctrl_latency = Param.Latency('11ns', "The latency experienced by" 196 "every packet regardless of size of packet") |
148 | 197 |
149 # Number of packets (not flits) to store at the response side of the HMC 150 # controller. 151 ctrl_buffer_size_rsp = Param.Unsigned(256, "Number of packets to buffer " 152 "at the HMC controller (response side)") | 198 # Number of parallel lanes in each serial link [1] 199 num_lanes_per_link = Param.Unsigned( 16, "Number of lanes per each link") |
153 | 200 |
154 # Latency of the HMC controller to process the packets 155 # (ClockDomain = Host clock domain) 156 ctrl_latency = Param.Cycles(4, "The number of cycles required for the " 157 " controller to process the packet") | 201 # Number of serial links [1] 202 num_serial_links = Param.Unsigned(4, "Number of serial links") |
158 | 203 |
159 # Wiring latency from the SoC crossbar to the HMC controller 160 ctrl_static_latency = Param.Latency('500ps', "Static latency of the HMC" 161 "controller") | 204 # speed of each lane of serial link - SerDes serial interface 10 Gb/s 205 serial_link_speed = Param.UInt64(10, "Gbs/s speed of each lane of" 206 "serial link") |
162 | 207 |
163 #*****************************PERFORMANCE MONITORING********************** | 208 #*****************************PERFORMANCE MONITORING************************ |
164 # The main monitor behind the HMC Controller | 209 # The main monitor behind the HMC Controller |
165 enable_global_monitor = Param.Bool(True, "The main monitor behind the " | 210 enable_global_monitor = Param.Bool(False, "The main monitor behind the " |
166 "HMC Controller") 167 168 # The link performance monitors | 211 "HMC Controller") 212 213 # The link performance monitors |
169 enable_link_monitor = Param.Bool(True, "The link monitors") | 214 enable_link_monitor = Param.Bool(False, "The link monitors" ) |
170 | 215 |
171# Create an HMC device and attach it to the current system 172def config_hmc(options, system): | 216 # link aggregator enable - put a cross between buffers & links 217 enable_link_aggr = Param.Bool(False, "The crossbar between port and " 218 "Link Controller") |
173 | 219 |
174 system.hmc = HMCSystem() | 220 enable_buff_div = Param.Bool(True, "Memory Range of Buffer is" 221 "divided between total range") |
175 | 222 |
176 system.buffer = Bridge(ranges=system.mem_ranges, 177 req_size=system.hmc.ctrl_buffer_size_req, 178 resp_size=system.hmc.ctrl_buffer_size_rsp, 179 delay=system.hmc.ctrl_static_latency) | 223 #*****************************HMC ARCHITECTURE ************************ 224 # Memory chunk for 16 vault - numbers of vault / number of crossbars 225 mem_chunk = Param.Unsigned(4, "Chunk of memory range for each cross bar " 226 "in arch 0") 227 228 # size of req buffer within crossbar, used for modelling extra latency 229 # when the reuqest go to non-local vault 230 xbar_buffer_size_req = Param.Unsigned(10, "Number of packets to buffer " 231 "at the request side of the crossbar") 232 233 # size of response buffer within crossbar, used for modelling extra latency 234 # when the response received from non-local vault 235 xbar_buffer_size_resp = Param.Unsigned(10, "Number of packets to buffer " 236 "at the response side of the crossbar") 237 238# configure host system with Serial Links 239def config_host_hmc(options, system): 240 241 system.hmc_host=HMCSystem() 242 |
180 try: | 243 try: |
181 system.hmc.enable_global_monitor = options.enable_global_monitor | 244 system.hmc_host.enable_global_monitor = options.enable_global_monitor |
182 except: 183 pass; 184 185 try: | 245 except: 246 pass; 247 248 try: |
186 system.hmc.enable_link_monitor = options.enable_link_monitor | 249 system.hmc_host.enable_link_monitor = options.enable_link_monitor |
187 except: 188 pass; 189 | 250 except: 251 pass; 252 |
190 system.membus.master = system.buffer.slave | 253 # Serial link Controller with 16 SerDes links at 10 Gbps 254 # with serial link ranges w.r.t to architecture 255 system.hmc_host.seriallink = [SerialLink(ranges = options.ser_ranges[i], 256 req_size=system.hmc_host.link_buffer_size_req, 257 resp_size=system.hmc_host.link_buffer_size_rsp, 258 num_lanes=system.hmc_host.num_lanes_per_link, 259 link_speed=system.hmc_host.serial_link_speed, 260 delay=system.hmc_host.total_ctrl_latency) 261 for i in xrange(system.hmc_host.num_serial_links)] |
191 | 262 |
192 # The HMC controller (Clock domain is the same as the host) 193 system.hmccontroller = HMCController(width=(system.hmc.num_lanes_per_link. 194 value * system.hmc.num_serial_links/8), 195 frontend_latency=system.hmc.ctrl_latency, 196 forward_latency=system.hmc.link_overhead, 197 response_latency=system.hmc.link_overhead) | 263 # enable global monitor 264 if system.hmc_host.enable_global_monitor: 265 system.hmc_host.lmonitor = [ CommMonitor() 266 for i in xrange(system.hmc_host.num_serial_links)] |
198 | 267 |
199 system.hmccontroller.clk_domain = SrcClockDomain(clock=system.hmc. 200 link_frequency, voltage_domain = VoltageDomain(voltage = '1V')) | 268 # set the clock frequency for serial link 269 for i in xrange(system.hmc_host.num_serial_links): 270 system.hmc_host.seriallink[i].clk_domain = SrcClockDomain(clock=system. 271 hmc_host.link_controller_frequency, voltage_domain= 272 VoltageDomain(voltage = '1V')) |
201 | 273 |
202 # Serial Links 203 system.hmc.seriallink =[ SerialLink(ranges = system.mem_ranges, 204 req_size=system.hmc.link_buffer_size_req, 205 resp_size=system.hmc.link_buffer_size_rsp, 206 num_lanes=system.hmc.num_lanes_per_link, 207 delay=system.hmc.link_latency) 208 for i in xrange(system.hmc.num_serial_links)] | 274 # Connect membus/traffic gen to Serial Link Controller for differrent HMC 275 # architectures 276 if options.arch == "distributed": 277 for i in xrange(system.hmc_host.num_links_controllers): 278 if system.hmc_host.enable_global_monitor: 279 system.membus.master = system.hmc_host.lmonitor[i].slave 280 system.hmc_host.lmonitor[i].master = \ 281 system.hmc_host.seriallink[i].slave 282 else: 283 system.membus.master = system.hmc_host.seriallink[i].slave 284 if options.arch == "mixed": 285 if system.hmc_host.enable_global_monitor: 286 system.membus.master = system.hmc_host.lmonitor[0].slave 287 system.hmc_host.lmonitor[0].master = \ 288 system.hmc_host.seriallink[0].slave |
209 | 289 |
210 if system.hmc.enable_link_monitor: 211 system.hmc.lmonitor = [ CommMonitor() 212 for i in xrange(system.hmc.num_serial_links)] | 290 system.membus.master = system.hmc_host.lmonitor[1].slave 291 system.hmc_host.lmonitor[1].master = \ 292 system.hmc_host.seriallink[1].slave |
213 | 293 |
214 # The HMC Crossbar located in its logic-base (LoB) 215 system.hmc.xbar = NoncoherentXBar(width = system.hmc.xbar_width, 216 frontend_latency=system.hmc.xbar_frontend_latency, 217 forward_latency=system.hmc.xbar_forward_latency, 218 response_latency=system.hmc.xbar_response_latency ) 219 system.hmc.xbar.clk_domain = SrcClockDomain(clock = 220 system.hmc.xbar_frequency, voltage_domain = 221 VoltageDomain(voltage = '1V')) | 294 system.tgen[2].port = system.hmc_host.lmonitor[2].slave 295 system.hmc_host.lmonitor[2].master = \ 296 system.hmc_host.seriallink[2].slave |
222 | 297 |
223 if system.hmc.enable_global_monitor: 224 system.gmonitor = CommMonitor() 225 system.buffer.master = system.gmonitor.slave 226 system.gmonitor.master = system.hmccontroller.slave 227 else: 228 system.hmccontroller.slave = system.buffer.master | 298 system.tgen[3].port = system.hmc_host.lmonitor[3].slave 299 system.hmc_host.lmonitor[3].master = \ 300 system.hmc_host.seriallink[3].slave 301 else: 302 system.membus.master = system.hmc_host.seriallink[0].slave 303 system.membus.master = system.hmc_host.seriallink[1].slave 304 system.tgen[2].port = system.hmc_host.seriallink[2].slave 305 system.tgen[3].port = system.hmc_host.seriallink[3].slave 306 if options.arch == "same" : 307 for i in xrange(system.hmc_host.num_links_controllers): 308 if system.hmc_host.enable_global_monitor: 309 system.tgen[i].port = system.hmc_host.lmonitor[i].slave 310 system.hmc_host.lmonitor[i].master = \ 311 system.hmc_host.seriallink[i].slave 312 else: 313 system.tgen[i].port = system.hmc_host.seriallink[i].slave |
229 | 314 |
230 for i in xrange(system.hmc.num_serial_links): 231 system.hmccontroller.master = system.hmc.seriallink[i].slave 232 system.hmc.seriallink[i].clk_domain = system.hmccontroller.clk_domain; 233 if system.hmc.enable_link_monitor: 234 system.hmc.seriallink[i].master = system.hmc.lmonitor[i].slave 235 system.hmc.lmonitor[i].master = system.hmc.xbar.slave | 315 return system 316 317# Create an HMC device and attach it to the current system 318def config_hmc(options, system, hmc_host): 319 320 # Create HMC device 321 system.hmc_dev = HMCSystem() 322 323 # Global monitor 324 try: 325 system.hmc_dev.enable_global_monitor = options.enable_global_monitor 326 except: 327 pass; 328 329 try: 330 system.hmc_dev.enable_link_monitor = options.enable_link_monitor 331 except: 332 pass; 333 334 335 if system.hmc_dev.enable_link_monitor: 336 system.hmc_dev.lmonitor = [ CommMonitor() 337 for i in xrange(system.hmc_dev.num_links_controllers)] 338 339 # 4 HMC Crossbars located in its logic-base (LoB) 340 system.hmc_dev.xbar = [ NoncoherentXBar(width=system.hmc_dev.xbar_width, 341 frontend_latency=system.hmc_dev.xbar_frontend_latency, 342 forward_latency=system.hmc_dev.xbar_forward_latency, 343 response_latency=system.hmc_dev.xbar_response_latency ) 344 for i in xrange(system.hmc_host.number_mem_crossbar)] 345 346 for i in xrange(system.hmc_dev.number_mem_crossbar): 347 system.hmc_dev.xbar[i].clk_domain = SrcClockDomain( 348 clock=system.hmc_dev.xbar_frequency,voltage_domain= 349 VoltageDomain(voltage='1V')) 350 351 # Attach 4 serial link to 4 crossbar/s 352 for i in xrange(system.hmc_dev.num_serial_links): 353 if system.hmc_dev.enable_link_monitor: 354 system.hmc_host.seriallink[i].master = \ 355 system.hmc_dev.lmonitor[i].slave 356 system.hmc_dev.lmonitor[i].master = system.hmc_dev.xbar[i].slave |
236 else: | 357 else: |
237 system.hmc.seriallink[i].master = system.hmc.xbar.slave | 358 system.hmc_host.seriallink[i].master = system.hmc_dev.xbar[i].slave 359 360 # Connecting xbar with each other for request arriving at the wrong xbar, 361 # then it will be forward to correct xbar. Bridge is used to connect xbars 362 if options.arch == "same": 363 numx = len(system.hmc_dev.xbar) 364 365 # create a list of buffers 366 system.hmc_dev.buffers = [ Bridge( 367 req_size=system.hmc_dev.xbar_buffer_size_req, 368 resp_size=system.hmc_dev.xbar_buffer_size_resp) 369 for i in xrange(numx * (system.hmc_dev.mem_chunk - 1))] 370 371 # Buffer iterator 372 it = iter(range(len(system.hmc_dev.buffers))) 373 374 # necesarry to add system_port to one of the xbar 375 system.system_port = system.hmc_dev.xbar[3].slave 376 377 # iterate over all the crossbars and connect them as required 378 for i in range(numx): 379 for j in range(numx): 380 # connect xbar to all other xbars except itself 381 if i != j: 382 # get the next index of buffer 383 index = it.next() 384 385 # Change the default values for ranges of bridge 386 system.hmc_dev.buffers[index].ranges = system.mem_ranges[ 387 j * int(system.hmc_dev.mem_chunk): 388 (j + 1) * int(system.hmc_dev.mem_chunk)] 389 390 # Connect the bridge between corssbars 391 system.hmc_dev.xbar[i].master = system.hmc_dev.buffers[ 392 index].slave 393 system.hmc_dev.buffers[ 394 index].master = system.hmc_dev.xbar[j].slave 395 else: 396 # Don't connect the xbar to itself 397 pass 398 399 # Two crossbars are connected to all other crossbars-Other 2 vault 400 # can only direct traffic to it local vaults 401 if options.arch == "mixed": 402 403 system.hmc_dev.buffer30 = Bridge(ranges=system.mem_ranges[0:4]) 404 system.hmc_dev.xbar[3].master = system.hmc_dev.buffer30.slave 405 system.hmc_dev.buffer30.master = system.hmc_dev.xbar[0].slave 406 407 system.hmc_dev.buffer31 = Bridge(ranges=system.mem_ranges[4:8]) 408 system.hmc_dev.xbar[3].master = system.hmc_dev.buffer31.slave 409 system.hmc_dev.buffer31.master = system.hmc_dev.xbar[1].slave 410 411 system.hmc_dev.buffer32 = Bridge(ranges=system.mem_ranges[8:12]) 412 system.hmc_dev.xbar[3].master = system.hmc_dev.buffer32.slave 413 system.hmc_dev.buffer32.master = system.hmc_dev.xbar[2].slave 414 415 416 system.hmc_dev.buffer20 = Bridge(ranges=system.mem_ranges[0:4]) 417 system.hmc_dev.xbar[2].master = system.hmc_dev.buffer20.slave 418 system.hmc_dev.buffer20.master = system.hmc_dev.xbar[0].slave 419 420 system.hmc_dev.buffer21 = Bridge(ranges=system.mem_ranges[4:8]) 421 system.hmc_dev.xbar[2].master = system.hmc_dev.buffer21.slave 422 system.hmc_dev.buffer21.master = system.hmc_dev.xbar[1].slave 423 424 system.hmc_dev.buffer23 = Bridge(ranges=system.mem_ranges[12:16]) 425 system.hmc_dev.xbar[2].master = system.hmc_dev.buffer23.slave 426 system.hmc_dev.buffer23.master = system.hmc_dev.xbar[3].slave 427 |