| HMC.py (11183:276ad9121192) | HMC.py (11187:854e61d5390e) |
|---|---|
| 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 70 unchanged lines hidden (view full) --- 79# them so a load distribution mechanism is required among them. 80 81import optparse 82 83import m5 84from m5.objects import * 85 86# A single Hybrid Memory Cube (HMC) | 1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 70 unchanged lines hidden (view full) --- 79# them so a load distribution mechanism is required among them. 80 81import optparse 82 83import m5 84from m5.objects import * 85 86# A single Hybrid Memory Cube (HMC) |
| 87class HMCSystem(SimOject): | 87class HMCSystem(SimObject): |
| 88 89 #*****************************CROSSBAR PARAMETERS************************* 90 # Flit size of the main interconnect [1] 91 xbar_width = Param.Unsigned( 32, "Data width of the main XBar (Bytes)") 92 93 # Clock frequency of the main interconnect [1] 94 # This crossbar, is placed on the logic-based of the HMC and it has its 95 # own voltage and clock domains, different from the DRAM dies or from the --- 143 unchanged lines hidden --- | 88 89 #*****************************CROSSBAR PARAMETERS************************* 90 # Flit size of the main interconnect [1] 91 xbar_width = Param.Unsigned( 32, "Data width of the main XBar (Bytes)") 92 93 # Clock frequency of the main interconnect [1] 94 # This crossbar, is placed on the logic-based of the HMC and it has its 95 # own voltage and clock domains, different from the DRAM dies or from the --- 143 unchanged lines hidden --- |