1#
2# Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# For use for simulation and test purposes only
6#
7# Redistribution and use in source and binary forms, with or without
8# modification, are permitted provided that the following conditions are met:
9#
10# 1. Redistributions of source code must retain the above copyright notice,
11# this list of conditions and the following disclaimer.
12#
13# 2. Redistributions in binary form must reproduce the above copyright notice,
14# this list of conditions and the following disclaimer in the documentation
15# and/or other materials provided with the distribution.
16#
17# 3. Neither the name of the copyright holder nor the names of its contributors
18# may be used to endorse or promote products derived from this software
19# without specific prior written permission.
20#
21# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31# POSSIBILITY OF SUCH DAMAGE.
32#
33# Author: Lisa Hsu
34#
35
36from __future__ import print_function
37
38# Configure the TLB hierarchy
39# Places which would probably need to be modified if you
40# want a different hierarchy are specified by a <Modify here .. >'
41# comment
42import m5
43from m5.objects import *
44
45def TLB_constructor(level):
46
47 constructor_call = "X86GPUTLB(size = options.L%(level)dTLBentries, \
48 assoc = options.L%(level)dTLBassoc, \
49 hitLatency = options.L%(level)dAccessLatency,\
50 missLatency2 = options.L%(level)dMissLatency,\
51 maxOutstandingReqs = options.L%(level)dMaxOutstandingReqs,\
52 accessDistance = options.L%(level)dAccessDistanceStat,\
53 clk_domain = SrcClockDomain(\
54 clock = options.GPUClock,\
55 voltage_domain = VoltageDomain(\
56 voltage = options.gpu_voltage)))" % locals()
57 return constructor_call
58
59def Coalescer_constructor(level):
60
61 constructor_call = "TLBCoalescer(probesPerCycle = \
62 options.L%(level)dProbesPerCycle, \
63 coalescingWindow = options.L%(level)dCoalescingWindow,\
64 disableCoalescing = options.L%(level)dDisableCoalescing,\
65 clk_domain = SrcClockDomain(\
66 clock = options.GPUClock,\
67 voltage_domain = VoltageDomain(\
68 voltage = options.gpu_voltage)))" % locals()
69 return constructor_call
70
71def create_TLB_Coalescer(options, my_level, my_index, TLB_name, Coalescer_name):
72 # arguments: options, TLB level, number of private structures for this Level,
73 # TLB name and Coalescer name
74 for i in xrange(my_index):
75 TLB_name.append(eval(TLB_constructor(my_level)))
76 Coalescer_name.append(eval(Coalescer_constructor(my_level)))
77
78def config_tlb_hierarchy(options, system, shader_idx):
79 n_cu = options.num_compute_units
80 # Make this configurable now, instead of the hard coded val. The dispatcher
81 # is always the last item in the system.cpu list.
82 dispatcher_idx = len(system.cpu) - 1
83
84 if options.TLB_config == "perLane":
85 num_TLBs = 64 * n_cu
86 elif options.TLB_config == "mono":
87 num_TLBs = 1
88 elif options.TLB_config == "perCU":
89 num_TLBs = n_cu
90 elif options.TLB_config == "2CU":
91 num_TLBs = n_cu >> 1
92 else:
93 print("Bad option for TLB Configuration.")
94 sys.exit(1)
95
96 #----------------------------------------------------------------------------------------
97 # A visual representation of the TLB hierarchy
98 # for ease of configuration
99 # < Modify here the width and the number of levels if you want a different configuration >
100 # width is the number of TLBs of the given type (i.e., D-TLB, I-TLB etc) for this level
101 L1 = [{'name': 'sqc', 'width': options.num_sqc, 'TLBarray': [], 'CoalescerArray': []},
102 {'name': 'dispatcher', 'width': 1, 'TLBarray': [], 'CoalescerArray': []},
103 {'name': 'l1', 'width': num_TLBs, 'TLBarray': [], 'CoalescerArray': []}]
104
105 L2 = [{'name': 'l2', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}]
106 L3 = [{'name': 'l3', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}]
107
108 TLB_hierarchy = [L1, L2, L3]
109
110 #----------------------------------------------------------------------------------------
111 # Create the hiearchy
112 # Call the appropriate constructors and add objects to the system
113
114 for i in xrange(len(TLB_hierarchy)):
115 hierarchy_level = TLB_hierarchy[i]
116 level = i+1
117 for TLB_type in hierarchy_level:
118 TLB_index = TLB_type['width']
119 TLB_array = TLB_type['TLBarray']
120 Coalescer_array = TLB_type['CoalescerArray']
121 # If the sim calls for a fixed L1 TLB size across CUs,
122 # override the TLB entries option
123 if options.tot_L1TLB_size:
124 options.L1TLBentries = options.tot_L1TLB_size / num_TLBs
125 if options.L1TLBassoc > options.L1TLBentries:
126 options.L1TLBassoc = options.L1TLBentries
127 # call the constructors for the TLB and the Coalescer
128 create_TLB_Coalescer(options, level, TLB_index,\
129 TLB_array, Coalescer_array)
130
131 system_TLB_name = TLB_type['name'] + '_tlb'
132 system_Coalescer_name = TLB_type['name'] + '_coalescer'
133
134 # add the different TLB levels to the system
135 # Modify here if you want to make the TLB hierarchy a child of
136 # the shader.
137 exec('system.%s = TLB_array' % system_TLB_name)
138 exec('system.%s = Coalescer_array' % system_Coalescer_name)
139
140 #===========================================================
141 # Specify the TLB hierarchy (i.e., port connections)
142 # All TLBs but the last level TLB need to have a memSidePort (master)
143 #===========================================================
144
145 # Each TLB is connected with its Coalescer through a single port.
146 # There is a one-to-one mapping of TLBs to Coalescers at a given level
147 # This won't be modified no matter what the hierarchy looks like.
148 for i in xrange(len(TLB_hierarchy)):
149 hierarchy_level = TLB_hierarchy[i]
150 level = i+1
151 for TLB_type in hierarchy_level:
152 name = TLB_type['name']
153 for index in range(TLB_type['width']):
154 exec('system.%s_coalescer[%d].master[0] = \
155 system.%s_tlb[%d].slave[0]' % \
156 (name, index, name, index))
157
158 # Connect the cpuSidePort (slave) of all the coalescers in level 1
159 # < Modify here if you want a different configuration >
160 for TLB_type in L1:
161 name = TLB_type['name']
162 num_TLBs = TLB_type['width']
163 if name == 'l1': # L1 D-TLBs
164 tlb_per_cu = num_TLBs / n_cu
165 for cu_idx in range(n_cu):
166 if tlb_per_cu:
167 for tlb in range(tlb_per_cu):
168 exec('system.cpu[%d].CUs[%d].translation_port[%d] = \
169 system.l1_coalescer[%d].slave[%d]' % \
170 (shader_idx, cu_idx, tlb, cu_idx*tlb_per_cu+tlb, 0))
171 else:
172 exec('system.cpu[%d].CUs[%d].translation_port[%d] = \
173 system.l1_coalescer[%d].slave[%d]' % \
174 (shader_idx, cu_idx, tlb_per_cu, cu_idx / (n_cu / num_TLBs), cu_idx % (n_cu / num_TLBs)))
175
176 elif name == 'dispatcher': # Dispatcher TLB
177 for index in range(TLB_type['width']):
178 exec('system.cpu[%d].translation_port = \
179 system.dispatcher_coalescer[%d].slave[0]' % \
180 (dispatcher_idx, index))
181 elif name == 'sqc': # I-TLB
182 for index in range(n_cu):
183 sqc_tlb_index = index / options.cu_per_sqc
184 sqc_tlb_port_id = index % options.cu_per_sqc
185 exec('system.cpu[%d].CUs[%d].sqc_tlb_port = \
186 system.sqc_coalescer[%d].slave[%d]' % \
187 (shader_idx, index, sqc_tlb_index, sqc_tlb_port_id))
188
189
190 # Connect the memSidePorts (masters) of all the TLBs with the
191 # cpuSidePorts (slaves) of the Coalescers of the next level
192 # < Modify here if you want a different configuration >
193 # L1 <-> L2
194 l2_coalescer_index = 0
195 for TLB_type in L1:
196 name = TLB_type['name']
197 for index in range(TLB_type['width']):
198 exec('system.%s_tlb[%d].master[0] = \
199 system.l2_coalescer[0].slave[%d]' % \
200 (name, index, l2_coalescer_index))
201 l2_coalescer_index += 1
202 # L2 <-> L3
203 system.l2_tlb[0].master[0] = system.l3_coalescer[0].slave[0]
204
205 return system
2# Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# For use for simulation and test purposes only
6#
7# Redistribution and use in source and binary forms, with or without
8# modification, are permitted provided that the following conditions are met:
9#
10# 1. Redistributions of source code must retain the above copyright notice,
11# this list of conditions and the following disclaimer.
12#
13# 2. Redistributions in binary form must reproduce the above copyright notice,
14# this list of conditions and the following disclaimer in the documentation
15# and/or other materials provided with the distribution.
16#
17# 3. Neither the name of the copyright holder nor the names of its contributors
18# may be used to endorse or promote products derived from this software
19# without specific prior written permission.
20#
21# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31# POSSIBILITY OF SUCH DAMAGE.
32#
33# Author: Lisa Hsu
34#
35
36from __future__ import print_function
37
38# Configure the TLB hierarchy
39# Places which would probably need to be modified if you
40# want a different hierarchy are specified by a <Modify here .. >'
41# comment
42import m5
43from m5.objects import *
44
45def TLB_constructor(level):
46
47 constructor_call = "X86GPUTLB(size = options.L%(level)dTLBentries, \
48 assoc = options.L%(level)dTLBassoc, \
49 hitLatency = options.L%(level)dAccessLatency,\
50 missLatency2 = options.L%(level)dMissLatency,\
51 maxOutstandingReqs = options.L%(level)dMaxOutstandingReqs,\
52 accessDistance = options.L%(level)dAccessDistanceStat,\
53 clk_domain = SrcClockDomain(\
54 clock = options.GPUClock,\
55 voltage_domain = VoltageDomain(\
56 voltage = options.gpu_voltage)))" % locals()
57 return constructor_call
58
59def Coalescer_constructor(level):
60
61 constructor_call = "TLBCoalescer(probesPerCycle = \
62 options.L%(level)dProbesPerCycle, \
63 coalescingWindow = options.L%(level)dCoalescingWindow,\
64 disableCoalescing = options.L%(level)dDisableCoalescing,\
65 clk_domain = SrcClockDomain(\
66 clock = options.GPUClock,\
67 voltage_domain = VoltageDomain(\
68 voltage = options.gpu_voltage)))" % locals()
69 return constructor_call
70
71def create_TLB_Coalescer(options, my_level, my_index, TLB_name, Coalescer_name):
72 # arguments: options, TLB level, number of private structures for this Level,
73 # TLB name and Coalescer name
74 for i in xrange(my_index):
75 TLB_name.append(eval(TLB_constructor(my_level)))
76 Coalescer_name.append(eval(Coalescer_constructor(my_level)))
77
78def config_tlb_hierarchy(options, system, shader_idx):
79 n_cu = options.num_compute_units
80 # Make this configurable now, instead of the hard coded val. The dispatcher
81 # is always the last item in the system.cpu list.
82 dispatcher_idx = len(system.cpu) - 1
83
84 if options.TLB_config == "perLane":
85 num_TLBs = 64 * n_cu
86 elif options.TLB_config == "mono":
87 num_TLBs = 1
88 elif options.TLB_config == "perCU":
89 num_TLBs = n_cu
90 elif options.TLB_config == "2CU":
91 num_TLBs = n_cu >> 1
92 else:
93 print("Bad option for TLB Configuration.")
94 sys.exit(1)
95
96 #----------------------------------------------------------------------------------------
97 # A visual representation of the TLB hierarchy
98 # for ease of configuration
99 # < Modify here the width and the number of levels if you want a different configuration >
100 # width is the number of TLBs of the given type (i.e., D-TLB, I-TLB etc) for this level
101 L1 = [{'name': 'sqc', 'width': options.num_sqc, 'TLBarray': [], 'CoalescerArray': []},
102 {'name': 'dispatcher', 'width': 1, 'TLBarray': [], 'CoalescerArray': []},
103 {'name': 'l1', 'width': num_TLBs, 'TLBarray': [], 'CoalescerArray': []}]
104
105 L2 = [{'name': 'l2', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}]
106 L3 = [{'name': 'l3', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}]
107
108 TLB_hierarchy = [L1, L2, L3]
109
110 #----------------------------------------------------------------------------------------
111 # Create the hiearchy
112 # Call the appropriate constructors and add objects to the system
113
114 for i in xrange(len(TLB_hierarchy)):
115 hierarchy_level = TLB_hierarchy[i]
116 level = i+1
117 for TLB_type in hierarchy_level:
118 TLB_index = TLB_type['width']
119 TLB_array = TLB_type['TLBarray']
120 Coalescer_array = TLB_type['CoalescerArray']
121 # If the sim calls for a fixed L1 TLB size across CUs,
122 # override the TLB entries option
123 if options.tot_L1TLB_size:
124 options.L1TLBentries = options.tot_L1TLB_size / num_TLBs
125 if options.L1TLBassoc > options.L1TLBentries:
126 options.L1TLBassoc = options.L1TLBentries
127 # call the constructors for the TLB and the Coalescer
128 create_TLB_Coalescer(options, level, TLB_index,\
129 TLB_array, Coalescer_array)
130
131 system_TLB_name = TLB_type['name'] + '_tlb'
132 system_Coalescer_name = TLB_type['name'] + '_coalescer'
133
134 # add the different TLB levels to the system
135 # Modify here if you want to make the TLB hierarchy a child of
136 # the shader.
137 exec('system.%s = TLB_array' % system_TLB_name)
138 exec('system.%s = Coalescer_array' % system_Coalescer_name)
139
140 #===========================================================
141 # Specify the TLB hierarchy (i.e., port connections)
142 # All TLBs but the last level TLB need to have a memSidePort (master)
143 #===========================================================
144
145 # Each TLB is connected with its Coalescer through a single port.
146 # There is a one-to-one mapping of TLBs to Coalescers at a given level
147 # This won't be modified no matter what the hierarchy looks like.
148 for i in xrange(len(TLB_hierarchy)):
149 hierarchy_level = TLB_hierarchy[i]
150 level = i+1
151 for TLB_type in hierarchy_level:
152 name = TLB_type['name']
153 for index in range(TLB_type['width']):
154 exec('system.%s_coalescer[%d].master[0] = \
155 system.%s_tlb[%d].slave[0]' % \
156 (name, index, name, index))
157
158 # Connect the cpuSidePort (slave) of all the coalescers in level 1
159 # < Modify here if you want a different configuration >
160 for TLB_type in L1:
161 name = TLB_type['name']
162 num_TLBs = TLB_type['width']
163 if name == 'l1': # L1 D-TLBs
164 tlb_per_cu = num_TLBs / n_cu
165 for cu_idx in range(n_cu):
166 if tlb_per_cu:
167 for tlb in range(tlb_per_cu):
168 exec('system.cpu[%d].CUs[%d].translation_port[%d] = \
169 system.l1_coalescer[%d].slave[%d]' % \
170 (shader_idx, cu_idx, tlb, cu_idx*tlb_per_cu+tlb, 0))
171 else:
172 exec('system.cpu[%d].CUs[%d].translation_port[%d] = \
173 system.l1_coalescer[%d].slave[%d]' % \
174 (shader_idx, cu_idx, tlb_per_cu, cu_idx / (n_cu / num_TLBs), cu_idx % (n_cu / num_TLBs)))
175
176 elif name == 'dispatcher': # Dispatcher TLB
177 for index in range(TLB_type['width']):
178 exec('system.cpu[%d].translation_port = \
179 system.dispatcher_coalescer[%d].slave[0]' % \
180 (dispatcher_idx, index))
181 elif name == 'sqc': # I-TLB
182 for index in range(n_cu):
183 sqc_tlb_index = index / options.cu_per_sqc
184 sqc_tlb_port_id = index % options.cu_per_sqc
185 exec('system.cpu[%d].CUs[%d].sqc_tlb_port = \
186 system.sqc_coalescer[%d].slave[%d]' % \
187 (shader_idx, index, sqc_tlb_index, sqc_tlb_port_id))
188
189
190 # Connect the memSidePorts (masters) of all the TLBs with the
191 # cpuSidePorts (slaves) of the Coalescers of the next level
192 # < Modify here if you want a different configuration >
193 # L1 <-> L2
194 l2_coalescer_index = 0
195 for TLB_type in L1:
196 name = TLB_type['name']
197 for index in range(TLB_type['width']):
198 exec('system.%s_tlb[%d].master[0] = \
199 system.l2_coalescer[0].slave[%d]' % \
200 (name, index, l2_coalescer_index))
201 l2_coalescer_index += 1
202 # L2 <-> L3
203 system.l2_tlb[0].master[0] = system.l3_coalescer[0].slave[0]
204
205 return system