FSConfig.py (9665:6dbdeee787cc) FSConfig.py (9707:1305bec2733f)
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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175 mdesc = SysConfig()
176 self.readfile = mdesc.script()
177 self.iobus = NoncoherentBus()
178 self.membus = MemBus()
179 self.bridge = Bridge(delay='50ns')
180 self.t1000 = T1000()
181 self.t1000.attachOnChipIO(self.membus)
182 self.t1000.attachIO(self.iobus)
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 166 unchanged lines hidden (view full) ---

175 mdesc = SysConfig()
176 self.readfile = mdesc.script()
177 self.iobus = NoncoherentBus()
178 self.membus = MemBus()
179 self.bridge = Bridge(delay='50ns')
180 self.t1000 = T1000()
181 self.t1000.attachOnChipIO(self.membus)
182 self.t1000.attachIO(self.iobus)
183 self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB'),
184 zero = True)
185 self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size ='256MB'),
186 zero = True)
183 self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB'))
184 self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size ='256MB'))
187 self.mem_ranges = [self.physmem.range, self.physmem2.range]
188 self.bridge.master = self.iobus.slave
189 self.bridge.slave = self.membus.master
190 self.physmem.port = self.membus.master
191 self.physmem2.port = self.membus.master
192 self.rom.port = self.membus.master
193 self.nvram.port = self.membus.master
194 self.hypervisor_desc.port = self.membus.master

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270 try:
271 self.realview.ide.disks = [self.cf0]
272 except:
273 self.realview.cf_ctrl.disks = [self.cf0]
274
275 if bare_metal:
276 # EOT character on UART will end the simulation
277 self.realview.uart.end_on_eot = True
185 self.mem_ranges = [self.physmem.range, self.physmem2.range]
186 self.bridge.master = self.iobus.slave
187 self.bridge.slave = self.membus.master
188 self.physmem.port = self.membus.master
189 self.physmem2.port = self.membus.master
190 self.rom.port = self.membus.master
191 self.nvram.port = self.membus.master
192 self.hypervisor_desc.port = self.membus.master

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268 try:
269 self.realview.ide.disks = [self.cf0]
270 except:
271 self.realview.cf_ctrl.disks = [self.cf0]
272
273 if bare_metal:
274 # EOT character on UART will end the simulation
275 self.realview.uart.end_on_eot = True
278 self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem())),
279 zero = True)
276 self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem())))
280 self.mem_ranges = [self.physmem.range]
281 else:
282 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
283 if dtb_filename is not None:
284 self.dtb_filename = dtb_filename
285 self.machine_type = machine_type
286 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
287 print "The currently selected ARM platforms doesn't support"

--- 288 unchanged lines hidden --- 		277 self.mem_ranges = [self.physmem.range]
278 else:
279 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
280 if dtb_filename is not None:
281 self.dtb_filename = dtb_filename
282 self.machine_type = machine_type
283 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
284 print "The currently selected ARM platforms doesn't support"

--- 288 unchanged lines hidden ---