FSConfig.py (9622:d351a723eb02) FSConfig.py (9665:6dbdeee787cc)
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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50 def childImage(self, ci):
51 self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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50 def childImage(self, ci):
51 self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
58def makeLinuxAlphaSystem(mem_mode, MemClass, mdesc = None):
59 IO_address_space_base = 0x80000000000
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70 self.iobus = NoncoherentBus()
71 self.membus = MemBus()
72 # By default the bridge responds to all addresses above the I/O
73 # base address (including the PCI config space)
74 self.bridge = Bridge(delay='50ns',
75 ranges = [AddrRange(IO_address_space_base, Addr.max)])
59 IO_address_space_base = 0x80000000000
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70 self.iobus = NoncoherentBus()
71 self.membus = MemBus()
72 # By default the bridge responds to all addresses above the I/O
73 # base address (including the PCI config space)
74 self.bridge = Bridge(delay='50ns',
75 ranges = [AddrRange(IO_address_space_base, Addr.max)])
76 self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
76 self.physmem = MemClass(range = AddrRange(mdesc.mem()))
77 self.mem_ranges = [self.physmem.range]
78 self.bridge.master = self.iobus.slave
79 self.bridge.slave = self.membus.master
80 self.physmem.port = self.membus.master
81 self.disk0 = CowIdeDisk(driveID='master')
82 self.disk2 = CowIdeDisk(driveID='master')
83 self.disk0.childImage(mdesc.disk())
84 self.disk2.childImage(disk('linux-bigswap2.img'))

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99 self.pal = binary('ts_osfpal')
100 self.console = binary('console')
101 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
102
103 self.system_port = self.membus.slave
104
105 return self
106
77 self.mem_ranges = [self.physmem.range]
78 self.bridge.master = self.iobus.slave
79 self.bridge.slave = self.membus.master
80 self.physmem.port = self.membus.master
81 self.disk0 = CowIdeDisk(driveID='master')
82 self.disk2 = CowIdeDisk(driveID='master')
83 self.disk0.childImage(mdesc.disk())
84 self.disk2.childImage(disk('linux-bigswap2.img'))

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99 self.pal = binary('ts_osfpal')
100 self.console = binary('console')
101 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
102
103 self.system_port = self.membus.slave
104
105 return self
106
107def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
107def makeLinuxAlphaRubySystem(mem_mode, MemClass, mdesc = None):
108 class BaseTsunami(Tsunami):
109 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
110 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
111 pci_func=0, pci_dev=0, pci_bus=0)
112
108 class BaseTsunami(Tsunami):
109 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
110 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
111 pci_func=0, pci_dev=0, pci_bus=0)
112
113 physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
113 physmem = MemClass(range = AddrRange(mdesc.mem()))
114 self = LinuxAlphaSystem(physmem = physmem)
115 self.mem_ranges = [self.physmem.range]
116 if not mdesc:
117 # generic system
118 mdesc = SysConfig()
119 self.readfile = mdesc.script()
120
121 # Create pio bus to connect all device pio ports to rubymem's pio port

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152 self.terminal = Terminal()
153 self.kernel = binary('vmlinux')
154 self.pal = binary('ts_osfpal')
155 self.console = binary('console')
156 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
157
158 return self
159
114 self = LinuxAlphaSystem(physmem = physmem)
115 self.mem_ranges = [self.physmem.range]
116 if not mdesc:
117 # generic system
118 mdesc = SysConfig()
119 self.readfile = mdesc.script()
120
121 # Create pio bus to connect all device pio ports to rubymem's pio port

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152 self.terminal = Terminal()
153 self.kernel = binary('vmlinux')
154 self.pal = binary('ts_osfpal')
155 self.console = binary('console')
156 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
157
158 return self
159
160def makeSparcSystem(mem_mode, mdesc = None):
160def makeSparcSystem(mem_mode, MemClass, mdesc = None):
161 # Constants from iob.cc and uart8250.cc
162 iob_man_addr = 0x9800000000
163 uart_pio_size = 8
164
165 class CowMmDisk(MmDisk):
166 image = CowDiskImage(child=RawDiskImage(read_only=True),
167 read_only=False)
168

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175 mdesc = SysConfig()
176 self.readfile = mdesc.script()
177 self.iobus = NoncoherentBus()
178 self.membus = MemBus()
179 self.bridge = Bridge(delay='50ns')
180 self.t1000 = T1000()
181 self.t1000.attachOnChipIO(self.membus)
182 self.t1000.attachIO(self.iobus)
161 # Constants from iob.cc and uart8250.cc
162 iob_man_addr = 0x9800000000
163 uart_pio_size = 8
164
165 class CowMmDisk(MmDisk):
166 image = CowDiskImage(child=RawDiskImage(read_only=True),
167 read_only=False)
168

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175 mdesc = SysConfig()
176 self.readfile = mdesc.script()
177 self.iobus = NoncoherentBus()
178 self.membus = MemBus()
179 self.bridge = Bridge(delay='50ns')
180 self.t1000 = T1000()
181 self.t1000.attachOnChipIO(self.membus)
182 self.t1000.attachIO(self.iobus)
183 self.physmem = SimpleDDR3(range = AddrRange(Addr('1MB'), size = '64MB'),
184 zero = True)
185 self.physmem2 = SimpleDDR3(range = AddrRange(Addr('2GB'), size ='256MB'),
186 zero = True)
183 self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB'),
184 zero = True)
185 self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size ='256MB'),
186 zero = True)
187 self.mem_ranges = [self.physmem.range, self.physmem2.range]
188 self.bridge.master = self.iobus.slave
189 self.bridge.slave = self.membus.master
190 self.physmem.port = self.membus.master
191 self.physmem2.port = self.membus.master
192 self.rom.port = self.membus.master
193 self.nvram.port = self.membus.master
194 self.hypervisor_desc.port = self.membus.master

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222 self.nvram_bin = binary('nvram1')
223 self.hypervisor_desc_bin = binary('1up-hv.bin')
224 self.partition_desc_bin = binary('1up-md.bin')
225
226 self.system_port = self.membus.slave
227
228 return self
229
187 self.mem_ranges = [self.physmem.range, self.physmem2.range]
188 self.bridge.master = self.iobus.slave
189 self.bridge.slave = self.membus.master
190 self.physmem.port = self.membus.master
191 self.physmem2.port = self.membus.master
192 self.rom.port = self.membus.master
193 self.nvram.port = self.membus.master
194 self.hypervisor_desc.port = self.membus.master

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222 self.nvram_bin = binary('nvram1')
223 self.hypervisor_desc_bin = binary('1up-hv.bin')
224 self.partition_desc_bin = binary('1up-md.bin')
225
226 self.system_port = self.membus.slave
227
228 return self
229
230def makeArmSystem(mem_mode, machine_type, mdesc = None, dtb_filename = None,
231 bare_metal=False):
230def makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None,
231 dtb_filename = None, bare_metal=False):
232 assert machine_type
233
234 if bare_metal:
235 self = ArmSystem()
236 else:
237 self = LinuxArmSystem()
238
239 if not mdesc:

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270 try:
271 self.realview.ide.disks = [self.cf0]
272 except:
273 self.realview.cf_ctrl.disks = [self.cf0]
274
275 if bare_metal:
276 # EOT character on UART will end the simulation
277 self.realview.uart.end_on_eot = True
232 assert machine_type
233
234 if bare_metal:
235 self = ArmSystem()
236 else:
237 self = LinuxArmSystem()
238
239 if not mdesc:

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270 try:
271 self.realview.ide.disks = [self.cf0]
272 except:
273 self.realview.cf_ctrl.disks = [self.cf0]
274
275 if bare_metal:
276 # EOT character on UART will end the simulation
277 self.realview.uart.end_on_eot = True
278 self.physmem = SimpleDDR3(range = AddrRange(Addr(mdesc.mem())),
279 zero = True)
278 self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem())),
279 zero = True)
280 self.mem_ranges = [self.physmem.range]
281 else:
282 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
283 if dtb_filename is not None:
284 self.dtb_filename = dtb_filename
285 self.machine_type = machine_type
286 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
287 print "The currently selected ARM platforms doesn't support"
288 print " the amount of DRAM you've selected. Please try"
289 print " another platform"
290 sys.exit(1)
291
292 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
293 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
294
280 self.mem_ranges = [self.physmem.range]
281 else:
282 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
283 if dtb_filename is not None:
284 self.dtb_filename = dtb_filename
285 self.machine_type = machine_type
286 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
287 print "The currently selected ARM platforms doesn't support"
288 print " the amount of DRAM you've selected. Please try"
289 print " another platform"
290 sys.exit(1)
291
292 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
293 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
294
295 self.physmem = SimpleDDR3(range =
296 AddrRange(self.realview.mem_start_addr,
297 size = mdesc.mem()),
298 conf_table_reported = True)
295 self.physmem = MemClass(range = AddrRange(self.realview.mem_start_addr,
296 size = mdesc.mem()),
297 conf_table_reported = True)
299 self.mem_ranges = [self.physmem.range]
300 self.realview.setupBootLoader(self.membus, self, binary)
301 self.gic_cpu_addr = self.realview.gic.cpu_addr
302 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
303
304 if mdesc.disk().lower().count('android'):
305 boot_flags += " init=/init "
306 self.boot_osflags = boot_flags

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312 self.terminal = Terminal()
313 self.vncserver = VncServer()
314
315 self.system_port = self.membus.slave
316
317 return self
318
319
298 self.mem_ranges = [self.physmem.range]
299 self.realview.setupBootLoader(self.membus, self, binary)
300 self.gic_cpu_addr = self.realview.gic.cpu_addr
301 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
302
303 if mdesc.disk().lower().count('android'):
304 boot_flags += " init=/init "
305 self.boot_osflags = boot_flags

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311 self.terminal = Terminal()
312 self.vncserver = VncServer()
313
314 self.system_port = self.membus.slave
315
316 return self
317
318
320def makeLinuxMipsSystem(mem_mode, mdesc = None):
319def makeLinuxMipsSystem(mem_mode, MemClass, mdesc = None):
321 class BaseMalta(Malta):
322 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
323 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
324 pci_func=0, pci_dev=0, pci_bus=0)
325
326 self = LinuxMipsSystem()
327 if not mdesc:
328 # generic system
329 mdesc = SysConfig()
330 self.readfile = mdesc.script()
331 self.iobus = NoncoherentBus()
332 self.membus = MemBus()
333 self.bridge = Bridge(delay='50ns')
320 class BaseMalta(Malta):
321 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
322 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
323 pci_func=0, pci_dev=0, pci_bus=0)
324
325 self = LinuxMipsSystem()
326 if not mdesc:
327 # generic system
328 mdesc = SysConfig()
329 self.readfile = mdesc.script()
330 self.iobus = NoncoherentBus()
331 self.membus = MemBus()
332 self.bridge = Bridge(delay='50ns')
334 self.physmem = SimpleDDR3(range = AddrRange('1GB'))
333 self.physmem = MemClass(range = AddrRange('1GB'))
335 self.mem_ranges = [self.physmem.range]
336 self.bridge.master = self.iobus.slave
337 self.bridge.slave = self.membus.master
338 self.physmem.port = self.membus.master
339 self.disk0 = CowIdeDisk(driveID='master')
340 self.disk2 = CowIdeDisk(driveID='master')
341 self.disk0.childImage(mdesc.disk())
342 self.disk2.childImage(disk('linux-bigswap2.img'))

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420 #
421 x86_sys.piobus.master = x86_sys.physmem.port
422 # add the ide to the list of dma devices that later need to attach to
423 # dma controllers
424 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
425 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
426
427
334 self.mem_ranges = [self.physmem.range]
335 self.bridge.master = self.iobus.slave
336 self.bridge.slave = self.membus.master
337 self.physmem.port = self.membus.master
338 self.disk0 = CowIdeDisk(driveID='master')
339 self.disk2 = CowIdeDisk(driveID='master')
340 self.disk0.childImage(mdesc.disk())
341 self.disk2.childImage(disk('linux-bigswap2.img'))

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419 #
420 x86_sys.piobus.master = x86_sys.physmem.port
421 # add the ide to the list of dma devices that later need to attach to
422 # dma controllers
423 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
424 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
425
426
428def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
427def makeX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, self = None,
428 Ruby = False):
429 if self == None:
430 self = X86System()
431
432 if not mdesc:
433 # generic system
434 mdesc = SysConfig()
435 self.readfile = mdesc.script()
436
437 self.mem_mode = mem_mode
438
439 # Physical memory
429 if self == None:
430 self = X86System()
431
432 if not mdesc:
433 # generic system
434 mdesc = SysConfig()
435 self.readfile = mdesc.script()
436
437 self.mem_mode = mem_mode
438
439 # Physical memory
440 self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem()))
440 self.physmem = MemClass(range = AddrRange(mdesc.mem()))
441 self.mem_ranges = [self.physmem.range]
442
443 # Platform
444 self.pc = Pc()
445
446 # Create and connect the busses required by each memory system
447 if Ruby:
448 connectX86RubySystem(self)

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516 base_entries.append(assign_to_apic)
517 assignISAInt(0, 2)
518 assignISAInt(1, 1)
519 for i in range(3, 15):
520 assignISAInt(i, i)
521 self.intel_mp_table.base_entries = base_entries
522 self.intel_mp_table.ext_entries = ext_entries
523
441 self.mem_ranges = [self.physmem.range]
442
443 # Platform
444 self.pc = Pc()
445
446 # Create and connect the busses required by each memory system
447 if Ruby:
448 connectX86RubySystem(self)

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516 base_entries.append(assign_to_apic)
517 assignISAInt(0, 2)
518 assignISAInt(1, 1)
519 for i in range(3, 15):
520 assignISAInt(i, i)
521 self.intel_mp_table.base_entries = base_entries
522 self.intel_mp_table.ext_entries = ext_entries
523
524def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
524def makeLinuxX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None,
525 Ruby = False):
525 self = LinuxX86System()
526
527 # Build up the x86 system and then specialize it for Linux
526 self = LinuxX86System()
527
528 # Build up the x86 system and then specialize it for Linux
528 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
529 makeX86System(mem_mode, MemClass, numCPUs, mdesc, self, Ruby)
529
530 # We assume below that there's at least 1MB of memory. We'll require 2
531 # just to avoid corner cases.
532 phys_mem_size = sum(map(lambda mem: mem.range.size(),
533 self.memories.unproxy(self)))
534 assert(phys_mem_size >= 0x200000)
535
536 self.e820_table.entries = \

--- 38 unchanged lines hidden --- 		530
531 # We assume below that there's at least 1MB of memory. We'll require 2
532 # just to avoid corner cases.
533 phys_mem_size = sum(map(lambda mem: mem.range.size(),
534 self.memories.unproxy(self)))
535 assert(phys_mem_size >= 0x200000)
536
537 self.e820_table.entries = \

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