FSConfig.py (9232:3bb99fab80d4) | FSConfig.py (9311:227d19399b51) |
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1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 59 unchanged lines hidden (view full) --- 68 mdesc = SysConfig() 69 self.readfile = mdesc.script() 70 self.iobus = NoncoherentBus() 71 self.membus = MemBus() 72 # By default the bridge responds to all addresses above the I/O 73 # base address (including the PCI config space) 74 self.bridge = Bridge(delay='50ns', 75 ranges = [AddrRange(IO_address_space_base, Addr.max)]) | 1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 59 unchanged lines hidden (view full) --- 68 mdesc = SysConfig() 69 self.readfile = mdesc.script() 70 self.iobus = NoncoherentBus() 71 self.membus = MemBus() 72 # By default the bridge responds to all addresses above the I/O 73 # base address (including the PCI config space) 74 self.bridge = Bridge(delay='50ns', 75 ranges = [AddrRange(IO_address_space_base, Addr.max)]) |
76 self.physmem = SimpleMemory(range = AddrRange(mdesc.mem())) | 76 self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem())) |
77 self.bridge.master = self.iobus.slave 78 self.bridge.slave = self.membus.master 79 self.physmem.port = self.membus.master 80 self.disk0 = CowIdeDisk(driveID='master') 81 self.disk2 = CowIdeDisk(driveID='master') 82 self.disk0.childImage(mdesc.disk()) 83 self.disk2.childImage(disk('linux-bigswap2.img')) 84 self.tsunami = BaseTsunami() --- 19 unchanged lines hidden (view full) --- 104 return self 105 106def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 107 class BaseTsunami(Tsunami): 108 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 109 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 110 pci_func=0, pci_dev=0, pci_bus=0) 111 | 77 self.bridge.master = self.iobus.slave 78 self.bridge.slave = self.membus.master 79 self.physmem.port = self.membus.master 80 self.disk0 = CowIdeDisk(driveID='master') 81 self.disk2 = CowIdeDisk(driveID='master') 82 self.disk0.childImage(mdesc.disk()) 83 self.disk2.childImage(disk('linux-bigswap2.img')) 84 self.tsunami = BaseTsunami() --- 19 unchanged lines hidden (view full) --- 104 return self 105 106def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 107 class BaseTsunami(Tsunami): 108 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 109 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 110 pci_func=0, pci_dev=0, pci_bus=0) 111 |
112 physmem = SimpleMemory(range = AddrRange(mdesc.mem())) | 112 physmem = SimpleDRAM(range = AddrRange(mdesc.mem())) |
113 self = LinuxAlphaSystem(physmem = physmem) 114 if not mdesc: 115 # generic system 116 mdesc = SysConfig() 117 self.readfile = mdesc.script() 118 119 # Create pio bus to connect all device pio ports to rubymem's pio port 120 self.piobus = NoncoherentBus() --- 52 unchanged lines hidden (view full) --- 173 mdesc = SysConfig() 174 self.readfile = mdesc.script() 175 self.iobus = NoncoherentBus() 176 self.membus = MemBus() 177 self.bridge = Bridge(delay='50ns') 178 self.t1000 = T1000() 179 self.t1000.attachOnChipIO(self.membus) 180 self.t1000.attachIO(self.iobus) | 113 self = LinuxAlphaSystem(physmem = physmem) 114 if not mdesc: 115 # generic system 116 mdesc = SysConfig() 117 self.readfile = mdesc.script() 118 119 # Create pio bus to connect all device pio ports to rubymem's pio port 120 self.piobus = NoncoherentBus() --- 52 unchanged lines hidden (view full) --- 173 mdesc = SysConfig() 174 self.readfile = mdesc.script() 175 self.iobus = NoncoherentBus() 176 self.membus = MemBus() 177 self.bridge = Bridge(delay='50ns') 178 self.t1000 = T1000() 179 self.t1000.attachOnChipIO(self.membus) 180 self.t1000.attachIO(self.iobus) |
181 self.physmem = SimpleMemory(range = AddrRange(Addr('1MB'), size = '64MB'), | 181 self.physmem = SimpleDRAM(range = AddrRange(Addr('1MB'), size = '64MB'), |
182 zero = True) | 182 zero = True) |
183 self.physmem2 = SimpleMemory(range = AddrRange(Addr('2GB'), size ='256MB'), | 183 self.physmem2 = SimpleDRAM(range = AddrRange(Addr('2GB'), size ='256MB'), |
184 zero = True) 185 self.bridge.master = self.iobus.slave 186 self.bridge.slave = self.membus.master 187 self.physmem.port = self.membus.master 188 self.physmem2.port = self.membus.master 189 self.rom.port = self.membus.master 190 self.nvram.port = self.membus.master 191 self.hypervisor_desc.port = self.membus.master --- 74 unchanged lines hidden (view full) --- 266 try: 267 self.realview.ide.disks = [self.cf0] 268 except: 269 self.realview.cf_ctrl.disks = [self.cf0] 270 271 if bare_metal: 272 # EOT character on UART will end the simulation 273 self.realview.uart.end_on_eot = True | 184 zero = True) 185 self.bridge.master = self.iobus.slave 186 self.bridge.slave = self.membus.master 187 self.physmem.port = self.membus.master 188 self.physmem2.port = self.membus.master 189 self.rom.port = self.membus.master 190 self.nvram.port = self.membus.master 191 self.hypervisor_desc.port = self.membus.master --- 74 unchanged lines hidden (view full) --- 266 try: 267 self.realview.ide.disks = [self.cf0] 268 except: 269 self.realview.cf_ctrl.disks = [self.cf0] 270 271 if bare_metal: 272 # EOT character on UART will end the simulation 273 self.realview.uart.end_on_eot = True |
274 self.physmem = SimpleMemory(range = AddrRange(Addr(mdesc.mem())), | 274 self.physmem = SimpleDRAM(range = AddrRange(Addr(mdesc.mem())), |
275 zero = True) 276 else: 277 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 278 self.machine_type = machine_type 279 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 280 print "The currently selected ARM platforms doesn't support" 281 print " the amount of DRAM you've selected. Please try" 282 print " another platform" 283 sys.exit(1) 284 285 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 286 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 287 | 275 zero = True) 276 else: 277 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 278 self.machine_type = machine_type 279 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 280 print "The currently selected ARM platforms doesn't support" 281 print " the amount of DRAM you've selected. Please try" 282 print " another platform" 283 sys.exit(1) 284 285 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 286 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 287 |
288 self.physmem = SimpleMemory(range = | 288 self.physmem = SimpleDRAM(range = |
289 AddrRange(self.realview.mem_start_addr, 290 size = mdesc.mem()), 291 conf_table_reported = True) 292 self.realview.setupBootLoader(self.membus, self, binary) 293 self.gic_cpu_addr = self.realview.gic.cpu_addr 294 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 295 296 if mdesc.disk().lower().count('android'): --- 21 unchanged lines hidden (view full) --- 318 self = LinuxMipsSystem() 319 if not mdesc: 320 # generic system 321 mdesc = SysConfig() 322 self.readfile = mdesc.script() 323 self.iobus = NoncoherentBus() 324 self.membus = MemBus() 325 self.bridge = Bridge(delay='50ns') | 289 AddrRange(self.realview.mem_start_addr, 290 size = mdesc.mem()), 291 conf_table_reported = True) 292 self.realview.setupBootLoader(self.membus, self, binary) 293 self.gic_cpu_addr = self.realview.gic.cpu_addr 294 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 295 296 if mdesc.disk().lower().count('android'): --- 21 unchanged lines hidden (view full) --- 318 self = LinuxMipsSystem() 319 if not mdesc: 320 # generic system 321 mdesc = SysConfig() 322 self.readfile = mdesc.script() 323 self.iobus = NoncoherentBus() 324 self.membus = MemBus() 325 self.bridge = Bridge(delay='50ns') |
326 self.physmem = SimpleMemory(range = AddrRange('1GB')) | 326 self.physmem = SimpleDRAM(range = AddrRange('1GB')) |
327 self.bridge.master = self.iobus.slave 328 self.bridge.slave = self.membus.master 329 self.physmem.port = self.membus.master 330 self.disk0 = CowIdeDisk(driveID='master') 331 self.disk2 = CowIdeDisk(driveID='master') 332 self.disk0.childImage(mdesc.disk()) 333 self.disk2.childImage(disk('linux-bigswap2.img')) 334 self.malta = BaseMalta() --- 88 unchanged lines hidden (view full) --- 423 if not mdesc: 424 # generic system 425 mdesc = SysConfig() 426 self.readfile = mdesc.script() 427 428 self.mem_mode = mem_mode 429 430 # Physical memory | 327 self.bridge.master = self.iobus.slave 328 self.bridge.slave = self.membus.master 329 self.physmem.port = self.membus.master 330 self.disk0 = CowIdeDisk(driveID='master') 331 self.disk2 = CowIdeDisk(driveID='master') 332 self.disk0.childImage(mdesc.disk()) 333 self.disk2.childImage(disk('linux-bigswap2.img')) 334 self.malta = BaseMalta() --- 88 unchanged lines hidden (view full) --- 423 if not mdesc: 424 # generic system 425 mdesc = SysConfig() 426 self.readfile = mdesc.script() 427 428 self.mem_mode = mem_mode 429 430 # Physical memory |
431 self.physmem = SimpleMemory(range = AddrRange(mdesc.mem())) | 431 self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem())) |
432 433 # Platform 434 self.pc = Pc() 435 436 # Create and connect the busses required by each memory system 437 if Ruby: 438 connectX86RubySystem(self) 439 else: --- 124 unchanged lines hidden --- | 432 433 # Platform 434 self.pc = Pc() 435 436 # Create and connect the busses required by each memory system 437 if Ruby: 438 connectX86RubySystem(self) 439 else: --- 124 unchanged lines hidden --- |