FSConfig.py (9060:ee4104e628f3) FSConfig.py (9164:d112473185ea)
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70 self.iobus = NoncoherentBus()
71 self.membus = MemBus()
72 # By default the bridge responds to all addresses above the I/O
73 # base address (including the PCI config space)
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70 self.iobus = NoncoherentBus()
71 self.membus = MemBus()
72 # By default the bridge responds to all addresses above the I/O
73 # base address (including the PCI config space)
74 self.bridge = Bridge(delay='50ns', nack_delay='4ns',
74 self.bridge = Bridge(delay='50ns',
75 ranges = [AddrRange(IO_address_space_base, Addr.max)])
76 self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
77 self.bridge.master = self.iobus.slave
78 self.bridge.slave = self.membus.master
79 self.physmem.port = self.membus.master
80 self.disk0 = CowIdeDisk(driveID='master')
81 self.disk2 = CowIdeDisk(driveID='master')
82 self.disk0.childImage(mdesc.disk())

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169
170 self = SparcSystem()
171 if not mdesc:
172 # generic system
173 mdesc = SysConfig()
174 self.readfile = mdesc.script()
175 self.iobus = NoncoherentBus()
176 self.membus = MemBus()
75 ranges = [AddrRange(IO_address_space_base, Addr.max)])
76 self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
77 self.bridge.master = self.iobus.slave
78 self.bridge.slave = self.membus.master
79 self.physmem.port = self.membus.master
80 self.disk0 = CowIdeDisk(driveID='master')
81 self.disk2 = CowIdeDisk(driveID='master')
82 self.disk0.childImage(mdesc.disk())

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169
170 self = SparcSystem()
171 if not mdesc:
172 # generic system
173 mdesc = SysConfig()
174 self.readfile = mdesc.script()
175 self.iobus = NoncoherentBus()
176 self.membus = MemBus()
177 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
177 self.bridge = Bridge(delay='50ns')
178 self.t1000 = T1000()
179 self.t1000.attachOnChipIO(self.membus)
180 self.t1000.attachIO(self.iobus)
181 self.physmem = SimpleMemory(range = AddrRange(Addr('1MB'), size = '64MB'),
182 zero = True)
183 self.physmem2 = SimpleMemory(range = AddrRange(Addr('2GB'), size ='256MB'),
184 zero = True)
185 self.bridge.master = self.iobus.slave

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235 if not mdesc:
236 # generic system
237 mdesc = SysConfig()
238
239 self.readfile = mdesc.script()
240 self.iobus = NoncoherentBus()
241 self.membus = MemBus()
242 self.membus.badaddr_responder.warn_access = "warn"
178 self.t1000 = T1000()
179 self.t1000.attachOnChipIO(self.membus)
180 self.t1000.attachIO(self.iobus)
181 self.physmem = SimpleMemory(range = AddrRange(Addr('1MB'), size = '64MB'),
182 zero = True)
183 self.physmem2 = SimpleMemory(range = AddrRange(Addr('2GB'), size ='256MB'),
184 zero = True)
185 self.bridge.master = self.iobus.slave

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235 if not mdesc:
236 # generic system
237 mdesc = SysConfig()
238
239 self.readfile = mdesc.script()
240 self.iobus = NoncoherentBus()
241 self.membus = MemBus()
242 self.membus.badaddr_responder.warn_access = "warn"
243 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
243 self.bridge = Bridge(delay='50ns')
244 self.bridge.master = self.iobus.slave
245 self.bridge.slave = self.membus.master
246
247 self.mem_mode = mem_mode
248
249 if machine_type == "RealView_PBX":
250 self.realview = RealViewPBX()
251 elif machine_type == "RealView_EB":

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317
318 self = LinuxMipsSystem()
319 if not mdesc:
320 # generic system
321 mdesc = SysConfig()
322 self.readfile = mdesc.script()
323 self.iobus = NoncoherentBus()
324 self.membus = MemBus()
244 self.bridge.master = self.iobus.slave
245 self.bridge.slave = self.membus.master
246
247 self.mem_mode = mem_mode
248
249 if machine_type == "RealView_PBX":
250 self.realview = RealViewPBX()
251 elif machine_type == "RealView_EB":

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317
318 self = LinuxMipsSystem()
319 if not mdesc:
320 # generic system
321 mdesc = SysConfig()
322 self.readfile = mdesc.script()
323 self.iobus = NoncoherentBus()
324 self.membus = MemBus()
325 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
325 self.bridge = Bridge(delay='50ns')
326 self.physmem = SimpleMemory(range = AddrRange('1GB'))
327 self.bridge.master = self.iobus.slave
328 self.bridge.slave = self.membus.master
329 self.physmem.port = self.membus.master
330 self.disk0 = CowIdeDisk(driveID='master')
331 self.disk2 = CowIdeDisk(driveID='master')
332 self.disk0.childImage(mdesc.disk())
333 self.disk2.childImage(disk('linux-bigswap2.img'))

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363 interrupts_address_space_base = 0xa000000000000000
364 APIC_range_size = 1 << 12;
365
366 x86_sys.membus = MemBus()
367 x86_sys.physmem.port = x86_sys.membus.master
368
369 # North Bridge
370 x86_sys.iobus = NoncoherentBus()
326 self.physmem = SimpleMemory(range = AddrRange('1GB'))
327 self.bridge.master = self.iobus.slave
328 self.bridge.slave = self.membus.master
329 self.physmem.port = self.membus.master
330 self.disk0 = CowIdeDisk(driveID='master')
331 self.disk2 = CowIdeDisk(driveID='master')
332 self.disk0.childImage(mdesc.disk())
333 self.disk2.childImage(disk('linux-bigswap2.img'))

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363 interrupts_address_space_base = 0xa000000000000000
364 APIC_range_size = 1 << 12;
365
366 x86_sys.membus = MemBus()
367 x86_sys.physmem.port = x86_sys.membus.master
368
369 # North Bridge
370 x86_sys.iobus = NoncoherentBus()
371 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
371 x86_sys.bridge = Bridge(delay='50ns')
372 x86_sys.bridge.master = x86_sys.iobus.slave
373 x86_sys.bridge.slave = x86_sys.membus.master
374 # Allow the bridge to pass through the IO APIC (two pages),
375 # everything in the IO address range up to the local APIC, and
376 # then the entire PCI address space and beyond
377 x86_sys.bridge.ranges = \
378 [
379 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
380 x86_sys.pc.south_bridge.io_apic.pio_addr +
381 APIC_range_size - 1),
382 AddrRange(IO_address_space_base,
383 interrupts_address_space_base - 1),
384 AddrRange(pci_config_address_space_base,
385 Addr.max)
386 ]
387
388 # Create a bridge from the IO bus to the memory bus to allow access to
389 # the local APIC (two pages)
372 x86_sys.bridge.master = x86_sys.iobus.slave
373 x86_sys.bridge.slave = x86_sys.membus.master
374 # Allow the bridge to pass through the IO APIC (two pages),
375 # everything in the IO address range up to the local APIC, and
376 # then the entire PCI address space and beyond
377 x86_sys.bridge.ranges = \
378 [
379 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
380 x86_sys.pc.south_bridge.io_apic.pio_addr +
381 APIC_range_size - 1),
382 AddrRange(IO_address_space_base,
383 interrupts_address_space_base - 1),
384 AddrRange(pci_config_address_space_base,
385 Addr.max)
386 ]
387
388 # Create a bridge from the IO bus to the memory bus to allow access to
389 # the local APIC (two pages)
390 x86_sys.apicbridge = Bridge(delay='50ns', nack_delay='4ns')
390 x86_sys.apicbridge = Bridge(delay='50ns')
391 x86_sys.apicbridge.slave = x86_sys.iobus.master
392 x86_sys.apicbridge.master = x86_sys.membus.slave
393 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
394 interrupts_address_space_base +
395 numCPUs * APIC_range_size
396 - 1)]
397
398 # connect the io bus

--- 163 unchanged lines hidden --- 		391 x86_sys.apicbridge.slave = x86_sys.iobus.master
392 x86_sys.apicbridge.master = x86_sys.membus.slave
393 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
394 interrupts_address_space_base +
395 numCPUs * APIC_range_size
396 - 1)]
397
398 # connect the io bus

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