FSConfig.py (8706:b1838faf3bcc) FSConfig.py (8713:2f1a3e335255)
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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51 self.image.child.image_file = ci
52
53class MemBus(Bus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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51 self.image.child.image_file = ci
52
53class MemBus(Bus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
59 IO_address_space_base = 0x80000000000
59 class BaseTsunami(Tsunami):
60 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
61 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
62 pci_func=0, pci_dev=0, pci_bus=0)
63
64 self = LinuxAlphaSystem()
65 if not mdesc:
66 # generic system
67 mdesc = SysConfig()
68 self.readfile = mdesc.script()
69 self.iobus = Bus(bus_id=0)
70 self.membus = MemBus(bus_id=1)
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70 self.iobus = Bus(bus_id=0)
71 self.membus = MemBus(bus_id=1)
71 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
72 # By default the bridge responds to all addresses above the I/O
73 # base address (including the PCI config space)
74 self.bridge = Bridge(delay='50ns', nack_delay='4ns',
75 ranges = [AddrRange(IO_address_space_base, Addr.max)])
72 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
76 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
73 self.bridge.side_a = self.iobus.port
74 self.bridge.side_b = self.membus.port
77 self.bridge.master = self.iobus.port
78 self.bridge.slave = self.membus.port
75 self.physmem.port = self.membus.port
76 self.disk0 = CowIdeDisk(driveID='master')
77 self.disk2 = CowIdeDisk(driveID='master')
78 self.disk0.childImage(mdesc.disk())
79 self.disk2.childImage(disk('linux-bigswap2.img'))
80 self.tsunami = BaseTsunami()
81 self.tsunami.attachIO(self.iobus)
82 self.tsunami.ide.pio = self.iobus.port

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141 self.kernel = binary('vmlinux')
142 self.pal = binary('ts_osfpal')
143 self.console = binary('console')
144 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
145
146 return self
147
148def makeSparcSystem(mem_mode, mdesc = None):
79 self.physmem.port = self.membus.port
80 self.disk0 = CowIdeDisk(driveID='master')
81 self.disk2 = CowIdeDisk(driveID='master')
82 self.disk0.childImage(mdesc.disk())
83 self.disk2.childImage(disk('linux-bigswap2.img'))
84 self.tsunami = BaseTsunami()
85 self.tsunami.attachIO(self.iobus)
86 self.tsunami.ide.pio = self.iobus.port

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145 self.kernel = binary('vmlinux')
146 self.pal = binary('ts_osfpal')
147 self.console = binary('console')
148 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
149
150 return self
151
152def makeSparcSystem(mem_mode, mdesc = None):
153 # Constants from iob.cc and uart8250.cc
154 iob_man_addr = 0x9800000000
155 uart_pio_size = 8
156
149 class CowMmDisk(MmDisk):
150 image = CowDiskImage(child=RawDiskImage(read_only=True),
151 read_only=False)
152
153 def childImage(self, ci):
154 self.image.child.image_file = ci
155
156 self = SparcSystem()

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161 self.iobus = Bus(bus_id=0)
162 self.membus = MemBus(bus_id=1)
163 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
164 self.t1000 = T1000()
165 self.t1000.attachOnChipIO(self.membus)
166 self.t1000.attachIO(self.iobus)
167 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
168 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
157 class CowMmDisk(MmDisk):
158 image = CowDiskImage(child=RawDiskImage(read_only=True),
159 read_only=False)
160
161 def childImage(self, ci):
162 self.image.child.image_file = ci
163
164 self = SparcSystem()

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169 self.iobus = Bus(bus_id=0)
170 self.membus = MemBus(bus_id=1)
171 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
172 self.t1000 = T1000()
173 self.t1000.attachOnChipIO(self.membus)
174 self.t1000.attachIO(self.iobus)
175 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
176 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
169 self.bridge.side_a = self.iobus.port
170 self.bridge.side_b = self.membus.port
177 self.bridge.master = self.iobus.port
178 self.bridge.slave = self.membus.port
171 self.physmem.port = self.membus.port
172 self.physmem2.port = self.membus.port
173 self.rom.port = self.membus.port
174 self.nvram.port = self.membus.port
175 self.hypervisor_desc.port = self.membus.port
176 self.partition_desc.port = self.membus.port
177 self.intrctrl = IntrControl()
178 self.disk0 = CowMmDisk()
179 self.disk0.childImage(disk('disk.s10hw2'))
180 self.disk0.pio = self.iobus.port
179 self.physmem.port = self.membus.port
180 self.physmem2.port = self.membus.port
181 self.rom.port = self.membus.port
182 self.nvram.port = self.membus.port
183 self.hypervisor_desc.port = self.membus.port
184 self.partition_desc.port = self.membus.port
185 self.intrctrl = IntrControl()
186 self.disk0 = CowMmDisk()
187 self.disk0.childImage(disk('disk.s10hw2'))
188 self.disk0.pio = self.iobus.port
189
190 # The puart0 and hvuart are placed on the IO bus, so create ranges
191 # for them. The remaining IO range is rather fragmented, so poke
192 # holes for the iob and partition descriptors etc.
193 self.bridge.ranges = \
194 [
195 AddrRange(self.t1000.puart0.pio_addr,
196 self.t1000.puart0.pio_addr + uart_pio_size - 1),
197 AddrRange(self.disk0.pio_addr,
198 self.t1000.fake_jbi.pio_addr +
199 self.t1000.fake_jbi.pio_size - 1),
200 AddrRange(self.t1000.fake_clk.pio_addr,
201 iob_man_addr - 1),
202 AddrRange(self.t1000.fake_l2_1.pio_addr,
203 self.t1000.fake_ssi.pio_addr +
204 self.t1000.fake_ssi.pio_size - 1),
205 AddrRange(self.t1000.hvuart.pio_addr,
206 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
207 ]
181 self.reset_bin = binary('reset_new.bin')
182 self.hypervisor_bin = binary('q_new.bin')
183 self.openboot_bin = binary('openboot_new.bin')
184 self.nvram_bin = binary('nvram1')
185 self.hypervisor_desc_bin = binary('1up-hv.bin')
186 self.partition_desc_bin = binary('1up-md.bin')
187
188 self.system_port = self.membus.port

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201 # generic system
202 mdesc = SysConfig()
203
204 self.readfile = mdesc.script()
205 self.iobus = Bus(bus_id=0)
206 self.membus = MemBus(bus_id=1)
207 self.membus.badaddr_responder.warn_access = "warn"
208 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
208 self.reset_bin = binary('reset_new.bin')
209 self.hypervisor_bin = binary('q_new.bin')
210 self.openboot_bin = binary('openboot_new.bin')
211 self.nvram_bin = binary('nvram1')
212 self.hypervisor_desc_bin = binary('1up-hv.bin')
213 self.partition_desc_bin = binary('1up-md.bin')
214
215 self.system_port = self.membus.port

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228 # generic system
229 mdesc = SysConfig()
230
231 self.readfile = mdesc.script()
232 self.iobus = Bus(bus_id=0)
233 self.membus = MemBus(bus_id=1)
234 self.membus.badaddr_responder.warn_access = "warn"
235 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
209 self.bridge.side_a = self.iobus.port
210 self.bridge.side_b = self.membus.port
236 self.bridge.master = self.iobus.port
237 self.bridge.slave = self.membus.port
211
212 self.mem_mode = mem_mode
213
214 if machine_type == "RealView_PBX":
215 self.realview = RealViewPBX()
216 elif machine_type == "RealView_EB":
217 self.realview = RealViewEB()
218 elif machine_type == "VExpress_ELT":

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256 self.gic_cpu_addr = self.realview.gic.cpu_addr
257 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
258
259 if mdesc.disk().lower().count('android'):
260 boot_flags += " init=/init "
261 self.boot_osflags = boot_flags
262
263 self.physmem.port = self.membus.port
238
239 self.mem_mode = mem_mode
240
241 if machine_type == "RealView_PBX":
242 self.realview = RealViewPBX()
243 elif machine_type == "RealView_EB":
244 self.realview = RealViewEB()
245 elif machine_type == "VExpress_ELT":

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283 self.gic_cpu_addr = self.realview.gic.cpu_addr
284 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
285
286 if mdesc.disk().lower().count('android'):
287 boot_flags += " init=/init "
288 self.boot_osflags = boot_flags
289
290 self.physmem.port = self.membus.port
264 self.realview.attachOnChipIO(self.membus)
291 self.realview.attachOnChipIO(self.membus, self.bridge)
265 self.realview.attachIO(self.iobus)
266 self.intrctrl = IntrControl()
267 self.terminal = Terminal()
268 self.vncserver = VncServer()
269
270 self.system_port = self.membus.port
271
272 return self

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282 if not mdesc:
283 # generic system
284 mdesc = SysConfig()
285 self.readfile = mdesc.script()
286 self.iobus = Bus(bus_id=0)
287 self.membus = MemBus(bus_id=1)
288 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
289 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
292 self.realview.attachIO(self.iobus)
293 self.intrctrl = IntrControl()
294 self.terminal = Terminal()
295 self.vncserver = VncServer()
296
297 self.system_port = self.membus.port
298
299 return self

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309 if not mdesc:
310 # generic system
311 mdesc = SysConfig()
312 self.readfile = mdesc.script()
313 self.iobus = Bus(bus_id=0)
314 self.membus = MemBus(bus_id=1)
315 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
316 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
290 self.bridge.side_a = self.iobus.port
291 self.bridge.side_b = self.membus.port
317 self.bridge.master = self.iobus.port
318 self.bridge.slave = self.membus.port
292 self.physmem.port = self.membus.port
293 self.disk0 = CowIdeDisk(driveID='master')
294 self.disk2 = CowIdeDisk(driveID='master')
295 self.disk0.childImage(mdesc.disk())
296 self.disk2.childImage(disk('linux-bigswap2.img'))
297 self.malta = BaseMalta()
298 self.malta.attachIO(self.iobus)
299 self.malta.ide.pio = self.iobus.port

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311
312 return self
313
314def x86IOAddress(port):
315 IO_address_space_base = 0x8000000000000000
316 return IO_address_space_base + port
317
318def connectX86ClassicSystem(x86_sys):
319 self.physmem.port = self.membus.port
320 self.disk0 = CowIdeDisk(driveID='master')
321 self.disk2 = CowIdeDisk(driveID='master')
322 self.disk0.childImage(mdesc.disk())
323 self.disk2.childImage(disk('linux-bigswap2.img'))
324 self.malta = BaseMalta()
325 self.malta.attachIO(self.iobus)
326 self.malta.ide.pio = self.iobus.port

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338
339 return self
340
341def x86IOAddress(port):
342 IO_address_space_base = 0x8000000000000000
343 return IO_address_space_base + port
344
345def connectX86ClassicSystem(x86_sys):
346 # Constants similar to x86_traits.hh
347 IO_address_space_base = 0x8000000000000000
348 pci_config_address_space_base = 0xc000000000000000
349 interrupts_address_space_base = 0xa000000000000000
350 APIC_range_size = 1 << 12;
351
319 x86_sys.membus = MemBus(bus_id=1)
320 x86_sys.physmem.port = x86_sys.membus.port
321
322 # North Bridge
323 x86_sys.iobus = Bus(bus_id=0)
324 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
352 x86_sys.membus = MemBus(bus_id=1)
353 x86_sys.physmem.port = x86_sys.membus.port
354
355 # North Bridge
356 x86_sys.iobus = Bus(bus_id=0)
357 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
325 x86_sys.bridge.side_a = x86_sys.iobus.port
326 x86_sys.bridge.side_b = x86_sys.membus.port
358 x86_sys.bridge.master = x86_sys.iobus.port
359 x86_sys.bridge.slave = x86_sys.membus.port
360 # Allow the bridge to pass through the IO APIC (two pages),
361 # everything in the IO address range up to the local APIC, and
362 # then the entire PCI address space and beyond
363 x86_sys.bridge.ranges = \
364 [
365 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
366 x86_sys.pc.south_bridge.io_apic.pio_addr +
367 APIC_range_size - 1),
368 AddrRange(IO_address_space_base,
369 interrupts_address_space_base - 1),
370 AddrRange(pci_config_address_space_base,
371 Addr.max)
372 ]
327
373
374 # Create a bridge from the IO bus to the memory bus to allow access to
375 # the local APIC (two pages)
376 x86_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns')
377 x86_sys.iobridge.slave = x86_sys.iobus.port
378 x86_sys.iobridge.master = x86_sys.membus.port
379 x86_sys.iobridge.ranges = [AddrRange(interrupts_address_space_base,
380 interrupts_address_space_base +
381 APIC_range_size - 1)]
382
328 # connect the io bus
329 x86_sys.pc.attachIO(x86_sys.iobus)
330
331 x86_sys.system_port = x86_sys.membus.port
332
333def connectX86RubySystem(x86_sys):
334 # North Bridge
335 x86_sys.piobus = Bus(bus_id=0)

--- 244 unchanged lines hidden --- 		383 # connect the io bus
384 x86_sys.pc.attachIO(x86_sys.iobus)
385
386 x86_sys.system_port = x86_sys.membus.port
387
388def connectX86RubySystem(x86_sys):
389 # North Bridge
390 x86_sys.piobus = Bus(bus_id=0)

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