| FSConfig.py (8287:45f3ac6b6a1c) | FSConfig.py (8323:fd20dcf1a9aa) |
|---|---|
| 1# Copyright (c) 2010 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 292 unchanged lines hidden (view full) --- 301 self.kernel = binary('mips/vmlinux') 302 self.console = binary('mips/console') 303 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 304 305 return self 306 307def x86IOAddress(port): 308 IO_address_space_base = 0x8000000000000000 | 1# Copyright (c) 2010 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 292 unchanged lines hidden (view full) --- 301 self.kernel = binary('mips/vmlinux') 302 self.console = binary('mips/console') 303 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 304 305 return self 306 307def x86IOAddress(port): 308 IO_address_space_base = 0x8000000000000000 |
| 309 return IO_address_space_base + port; | 309 return IO_address_space_base + port |
| 310 311def connectX86ClassicSystem(x86_sys): 312 x86_sys.membus = MemBus(bus_id=1) 313 x86_sys.physmem.port = x86_sys.membus.port 314 315 # North Bridge 316 x86_sys.iobus = Bus(bus_id=0) 317 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') --- 52 unchanged lines hidden (view full) --- 370 disk2.childImage(disk('linux-bigswap2.img')) 371 self.pc.south_bridge.ide.disks = [disk0, disk2] 372 373 # Add in a Bios information structure. 374 structures = [X86SMBiosBiosInformation()] 375 self.smbios_table.structures = structures 376 377 # Set up the Intel MP table | 310 311def connectX86ClassicSystem(x86_sys): 312 x86_sys.membus = MemBus(bus_id=1) 313 x86_sys.physmem.port = x86_sys.membus.port 314 315 # North Bridge 316 x86_sys.iobus = Bus(bus_id=0) 317 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') --- 52 unchanged lines hidden (view full) --- 370 disk2.childImage(disk('linux-bigswap2.img')) 371 self.pc.south_bridge.ide.disks = [disk0, disk2] 372 373 # Add in a Bios information structure. 374 structures = [X86SMBiosBiosInformation()] 375 self.smbios_table.structures = structures 376 377 # Set up the Intel MP table |
| 378 base_entries = [] 379 ext_entries = [] |
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| 378 for i in xrange(numCPUs): 379 bp = X86IntelMPProcessor( 380 local_apic_id = i, 381 local_apic_version = 0x14, 382 enable = True, 383 bootstrap = (i == 0)) | 380 for i in xrange(numCPUs): 381 bp = X86IntelMPProcessor( 382 local_apic_id = i, 383 local_apic_version = 0x14, 384 enable = True, 385 bootstrap = (i == 0)) |
| 384 self.intel_mp_table.add_entry(bp) | 386 base_entries.append(bp) |
| 385 io_apic = X86IntelMPIOAPIC( 386 id = numCPUs, 387 version = 0x11, 388 enable = True, 389 address = 0xfec00000) 390 self.pc.south_bridge.io_apic.apic_id = io_apic.id | 387 io_apic = X86IntelMPIOAPIC( 388 id = numCPUs, 389 version = 0x11, 390 enable = True, 391 address = 0xfec00000) 392 self.pc.south_bridge.io_apic.apic_id = io_apic.id |
| 391 self.intel_mp_table.add_entry(io_apic) | 393 base_entries.append(io_apic) |
| 392 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') | 394 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') |
| 393 self.intel_mp_table.add_entry(isa_bus) | 395 base_entries.append(isa_bus) |
| 394 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') | 396 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') |
| 395 self.intel_mp_table.add_entry(pci_bus) | 397 base_entries.append(pci_bus) |
| 396 connect_busses = X86IntelMPBusHierarchy(bus_id=0, 397 subtractive_decode=True, parent_bus=1) | 398 connect_busses = X86IntelMPBusHierarchy(bus_id=0, 399 subtractive_decode=True, parent_bus=1) |
| 398 self.intel_mp_table.add_entry(connect_busses) | 400 ext_entries.append(connect_busses) |
| 399 pci_dev4_inta = X86IntelMPIOIntAssignment( 400 interrupt_type = 'INT', 401 polarity = 'ConformPolarity', 402 trigger = 'ConformTrigger', 403 source_bus_id = 1, 404 source_bus_irq = 0 + (4 << 2), 405 dest_io_apic_id = io_apic.id, 406 dest_io_apic_intin = 16) | 401 pci_dev4_inta = X86IntelMPIOIntAssignment( 402 interrupt_type = 'INT', 403 polarity = 'ConformPolarity', 404 trigger = 'ConformTrigger', 405 source_bus_id = 1, 406 source_bus_irq = 0 + (4 << 2), 407 dest_io_apic_id = io_apic.id, 408 dest_io_apic_intin = 16) |
| 407 self.intel_mp_table.add_entry(pci_dev4_inta); | 409 base_entries.append(pci_dev4_inta) |
| 408 def assignISAInt(irq, apicPin): 409 assign_8259_to_apic = X86IntelMPIOIntAssignment( 410 interrupt_type = 'ExtInt', 411 polarity = 'ConformPolarity', 412 trigger = 'ConformTrigger', 413 source_bus_id = 0, 414 source_bus_irq = irq, 415 dest_io_apic_id = io_apic.id, 416 dest_io_apic_intin = 0) | 410 def assignISAInt(irq, apicPin): 411 assign_8259_to_apic = X86IntelMPIOIntAssignment( 412 interrupt_type = 'ExtInt', 413 polarity = 'ConformPolarity', 414 trigger = 'ConformTrigger', 415 source_bus_id = 0, 416 source_bus_irq = irq, 417 dest_io_apic_id = io_apic.id, 418 dest_io_apic_intin = 0) |
| 417 self.intel_mp_table.add_entry(assign_8259_to_apic) | 419 base_entries.append(assign_8259_to_apic) |
| 418 assign_to_apic = X86IntelMPIOIntAssignment( 419 interrupt_type = 'INT', 420 polarity = 'ConformPolarity', 421 trigger = 'ConformTrigger', 422 source_bus_id = 0, 423 source_bus_irq = irq, 424 dest_io_apic_id = io_apic.id, 425 dest_io_apic_intin = apicPin) | 420 assign_to_apic = X86IntelMPIOIntAssignment( 421 interrupt_type = 'INT', 422 polarity = 'ConformPolarity', 423 trigger = 'ConformTrigger', 424 source_bus_id = 0, 425 source_bus_irq = irq, 426 dest_io_apic_id = io_apic.id, 427 dest_io_apic_intin = apicPin) |
| 426 self.intel_mp_table.add_entry(assign_to_apic) | 428 base_entries.append(assign_to_apic) |
| 427 assignISAInt(0, 2) 428 assignISAInt(1, 1) 429 for i in range(3, 15): 430 assignISAInt(i, i) | 429 assignISAInt(0, 2) 430 assignISAInt(1, 1) 431 for i in range(3, 15): 432 assignISAInt(i, i) |
| 433 self.intel_mp_table.base_entries = base_entries 434 self.intel_mp_table.ext_entries = ext_entries |
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| 431 432def setWorkCountOptions(system, options): 433 if options.work_item_id != None: 434 system.work_item_id = options.work_item_id 435 if options.work_begin_cpu_id_exit != None: 436 system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 437 if options.work_end_exit_count != None: 438 system.work_end_exit_count = options.work_end_exit_count --- 12 unchanged lines hidden (view full) --- 451 452 # Build up the x86 system and then specialize it for Linux 453 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 454 455 # We assume below that there's at least 1MB of memory. We'll require 2 456 # just to avoid corner cases. 457 assert(self.physmem.range.second.getValue() >= 0x200000) 458 | 435 436def setWorkCountOptions(system, options): 437 if options.work_item_id != None: 438 system.work_item_id = options.work_item_id 439 if options.work_begin_cpu_id_exit != None: 440 system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 441 if options.work_end_exit_count != None: 442 system.work_end_exit_count = options.work_end_exit_count --- 12 unchanged lines hidden (view full) --- 455 456 # Build up the x86 system and then specialize it for Linux 457 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 458 459 # We assume below that there's at least 1MB of memory. We'll require 2 460 # just to avoid corner cases. 461 assert(self.physmem.range.second.getValue() >= 0x200000) 462 |
| 459 # Mark the first megabyte of memory as reserved 460 self.e820_table.entries.append(X86E820Entry( 461 addr = 0, 462 size = '1MB', 463 range_type = 2)) 464 465 # Mark the rest as available 466 self.e820_table.entries.append(X86E820Entry( 467 addr = 0x100000, | 463 self.e820_table.entries = \ 464 [ 465 # Mark the first megabyte of memory as reserved 466 X86E820Entry(addr = 0, size = '1MB', range_type = 2), 467 # Mark the rest as available 468 X86E820Entry(addr = 0x100000, |
| 468 size = '%dB' % (self.physmem.range.second - 0x100000 + 1), | 469 size = '%dB' % (self.physmem.range.second - 0x100000 + 1), |
| 469 range_type = 1)) | 470 range_type = 1) 471 ] |
| 470 471 # Command line 472 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 473 'root=/dev/hda1' 474 return self 475 476 477def makeDualRoot(testSystem, driveSystem, dumpfile): --- 82 unchanged lines hidden --- | 472 473 # Command line 474 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 475 'root=/dev/hda1' 476 return self 477 478 479def makeDualRoot(testSystem, driveSystem, dumpfile): --- 82 unchanged lines hidden --- |