| FSConfig.py (8061:08e91664adac) | FSConfig.py (8145:21e4f3a569fb) |
|---|---|
| 1# Copyright (c) 2010 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 187 unchanged lines hidden (view full) --- 196 # generic system 197 mdesc = SysConfig() 198 199 self.readfile = mdesc.script() 200 self.iobus = Bus(bus_id=0) 201 self.membus = MemBus(bus_id=1) 202 self.membus.badaddr_responder.warn_access = "warn" 203 self.bridge = Bridge(delay='50ns', nack_delay='4ns') | 1# Copyright (c) 2010 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 187 unchanged lines hidden (view full) --- 196 # generic system 197 mdesc = SysConfig() 198 199 self.readfile = mdesc.script() 200 self.iobus = Bus(bus_id=0) 201 self.membus = MemBus(bus_id=1) 202 self.membus.badaddr_responder.warn_access = "warn" 203 self.bridge = Bridge(delay='50ns', nack_delay='4ns') |
| 204 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True) 205 self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'), 206 file = disk('ael-arm.ext2')) | |
| 207 self.bridge.side_a = self.iobus.port 208 self.bridge.side_b = self.membus.port | 204 self.bridge.side_a = self.iobus.port 205 self.bridge.side_b = self.membus.port |
| 209 self.physmem.port = self.membus.port 210 self.diskmem.port = self.membus.port | |
| 211 212 self.mem_mode = mem_mode 213 214 #self.cf0 = CowIdeDisk(driveID='master') 215 #self.cf0.childImage(mdesc.disk()) 216 #self.cf_ctrl = IdeController(disks=[self.cf0], 217 # pci_func = 0, pci_dev = 0, pci_bus = 0, 218 # io_shift = 1, ctrl_offset = 2, Command = 0x1, --- 8 unchanged lines hidden (view full) --- 227 self.realview = RealViewEB() 228 else: 229 print "Unknown Machine Type" 230 sys.exit(1) 231 232 if bare_metal: 233 # EOT character on UART will end the simulation 234 self.realview.uart.end_on_eot = True | 206 207 self.mem_mode = mem_mode 208 209 #self.cf0 = CowIdeDisk(driveID='master') 210 #self.cf0.childImage(mdesc.disk()) 211 #self.cf_ctrl = IdeController(disks=[self.cf0], 212 # pci_func = 0, pci_dev = 0, pci_bus = 0, 213 # io_shift = 1, ctrl_offset = 2, Command = 0x1, --- 8 unchanged lines hidden (view full) --- 222 self.realview = RealViewEB() 223 else: 224 print "Unknown Machine Type" 225 sys.exit(1) 226 227 if bare_metal: 228 # EOT character on UART will end the simulation 229 self.realview.uart.end_on_eot = True |
| 230 self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')), zero = True) |
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| 235 else: | 231 else: |
| 232 self.physmem = PhysicalMemory(range = AddrRange(Addr('128MB')), zero = True) 233 self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'), 234 file = disk('ael-arm.ext2')) 235 self.diskmem.port = self.membus.port |
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| 236 self.machine_type = machine_type 237 self.kernel = binary('vmlinux.arm') 238 self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0' + \ 239 ' lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000' + \ 240 ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0' 241 | 236 self.machine_type = machine_type 237 self.kernel = binary('vmlinux.arm') 238 self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0' + \ 239 ' lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000' + \ 240 ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0' 241 |
| 242 self.physmem.port = self.membus.port |
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| 242 self.realview.attachOnChipIO(self.membus) 243 self.realview.attachIO(self.iobus) 244 245 self.intrctrl = IntrControl() 246 self.terminal = Terminal() 247 self.vncserver = VncServer() 248 249 return self --- 292 unchanged lines hidden --- | 243 self.realview.attachOnChipIO(self.membus) 244 self.realview.attachIO(self.iobus) 245 246 self.intrctrl = IntrControl() 247 self.terminal = Terminal() 248 self.vncserver = VncServer() 249 250 return self --- 292 unchanged lines hidden --- |