| FSConfig.py (7633:d8112aa18a1b) | FSConfig.py (7730:982b4c6c1470) |
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| 1# Copyright (c) 2010 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 186 unchanged lines hidden (view full) --- 195 mdesc = SysConfig() 196 197 self.readfile = mdesc.script() 198 self.iobus = Bus(bus_id=0) 199 self.membus = MemBus(bus_id=1) 200 self.membus.badaddr_responder.warn_access = "warn" 201 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 202 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True) | 1# Copyright (c) 2010 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 186 unchanged lines hidden (view full) --- 195 mdesc = SysConfig() 196 197 self.readfile = mdesc.script() 198 self.iobus = Bus(bus_id=0) 199 self.membus = MemBus(bus_id=1) 200 self.membus.badaddr_responder.warn_access = "warn" 201 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 202 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True) |
| 203 self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'), 204 file = disk('ael-arm.ext2')) |
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| 203 self.bridge.side_a = self.iobus.port 204 self.bridge.side_b = self.membus.port 205 self.physmem.port = self.membus.port | 205 self.bridge.side_a = self.iobus.port 206 self.bridge.side_b = self.membus.port 207 self.physmem.port = self.membus.port |
| 208 self.diskmem.port = self.membus.port |
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| 206 207 self.mem_mode = mem_mode 208 209 if machine_type == "RealView_PBX": 210 self.realview = RealViewPBX() 211 elif machine_type == "RealView_EB": 212 self.realview = RealViewEB() 213 else: --- 5 unchanged lines hidden (view full) --- 219 elif bare_metal: 220 self.realview.uart.end_on_eot = True 221 222 self.realview.attachOnChipIO(self.membus) 223 self.realview.attachIO(self.iobus) 224 225 self.intrctrl = IntrControl() 226 self.terminal = Terminal() | 209 210 self.mem_mode = mem_mode 211 212 if machine_type == "RealView_PBX": 213 self.realview = RealViewPBX() 214 elif machine_type == "RealView_EB": 215 self.realview = RealViewEB() 216 else: --- 5 unchanged lines hidden (view full) --- 222 elif bare_metal: 223 self.realview.uart.end_on_eot = True 224 225 self.realview.attachOnChipIO(self.membus) 226 self.realview.attachIO(self.iobus) 227 228 self.intrctrl = IntrControl() 229 self.terminal = Terminal() |
| 227 self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps' | 230 self.kernel = binary('vmlinux.arm') 231 self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480' + \ 232 ' norandmaps slram=slram0,0x8000000,+0x8000000' + \ 233 ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0' |
| 228 229 return self 230 231 232def makeLinuxMipsSystem(mem_mode, mdesc = None): 233 class BaseMalta(Malta): 234 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 235 ide = IdeController(disks=[Parent.disk0, Parent.disk2], --- 244 unchanged lines hidden --- | 234 235 return self 236 237 238def makeLinuxMipsSystem(mem_mode, mdesc = None): 239 class BaseMalta(Malta): 240 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 241 ide = IdeController(disks=[Parent.disk0, Parent.disk2], --- 244 unchanged lines hidden --- |