FSConfig.py (6122:9af6fb59752f) | FSConfig.py (6135:9327451a8e7a) |
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1# Copyright (c) 2006-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 150 unchanged lines hidden (view full) --- 159 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 160 161 return self 162 163def x86IOAddress(port): 164 IO_address_space_base = 0x8000000000000000 165 return IO_address_space_base + port; 166 | 1# Copyright (c) 2006-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 150 unchanged lines hidden (view full) --- 159 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 160 161 return self 162 163def x86IOAddress(port): 164 IO_address_space_base = 0x8000000000000000 165 return IO_address_space_base + port; 166 |
167def makeX86System(mem_mode, mdesc = None, self = None): | 167def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None): |
168 if self == None: 169 self = X86System() 170 171 if not mdesc: 172 # generic system 173 mdesc = SysConfig() 174 mdesc.diskname = 'x86root.img' 175 self.readfile = mdesc.script() --- 22 unchanged lines hidden (view full) --- 198 disk2.childImage(disk('linux-bigswap2.img')) 199 self.pc.south_bridge.ide.disks = [disk0, disk2] 200 201 # Add in a Bios information structure. 202 structures = [X86SMBiosBiosInformation()] 203 self.smbios_table.structures = structures 204 205 # Set up the Intel MP table | 168 if self == None: 169 self = X86System() 170 171 if not mdesc: 172 # generic system 173 mdesc = SysConfig() 174 mdesc.diskname = 'x86root.img' 175 self.readfile = mdesc.script() --- 22 unchanged lines hidden (view full) --- 198 disk2.childImage(disk('linux-bigswap2.img')) 199 self.pc.south_bridge.ide.disks = [disk0, disk2] 200 201 # Add in a Bios information structure. 202 structures = [X86SMBiosBiosInformation()] 203 self.smbios_table.structures = structures 204 205 # Set up the Intel MP table |
206 bp = X86IntelMPProcessor( 207 local_apic_id = 0, 208 local_apic_version = 0x14, 209 enable = True, 210 bootstrap = True) 211 self.intel_mp_table.add_entry(bp) | 206 for i in xrange(numCPUs): 207 bp = X86IntelMPProcessor( 208 local_apic_id = i, 209 local_apic_version = 0x14, 210 enable = True, 211 bootstrap = (i == 0)) 212 self.intel_mp_table.add_entry(bp) |
212 io_apic = X86IntelMPIOAPIC( | 213 io_apic = X86IntelMPIOAPIC( |
213 id = 1, | 214 id = numCPUs, |
214 version = 0x11, 215 enable = True, 216 address = 0xfec00000) | 215 version = 0x11, 216 enable = True, 217 address = 0xfec00000) |
218 self.pc.south_bridge.io_apic.apic_id = io_apic.id |
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217 self.intel_mp_table.add_entry(io_apic) 218 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 219 self.intel_mp_table.add_entry(isa_bus) 220 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 221 self.intel_mp_table.add_entry(pci_bus) 222 connect_busses = X86IntelMPBusHierarchy(bus_id=0, 223 subtractive_decode=True, parent_bus=1) 224 self.intel_mp_table.add_entry(connect_busses) 225 pci_dev4_inta = X86IntelMPIOIntAssignment( 226 interrupt_type = 'INT', 227 polarity = 'ConformPolarity', 228 trigger = 'ConformTrigger', 229 source_bus_id = 1, 230 source_bus_irq = 0 + (4 << 2), 231 dest_io_apic_id = io_apic.id, 232 dest_io_apic_intin = 16) 233 self.intel_mp_table.add_entry(pci_dev4_inta); | 219 self.intel_mp_table.add_entry(io_apic) 220 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 221 self.intel_mp_table.add_entry(isa_bus) 222 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 223 self.intel_mp_table.add_entry(pci_bus) 224 connect_busses = X86IntelMPBusHierarchy(bus_id=0, 225 subtractive_decode=True, parent_bus=1) 226 self.intel_mp_table.add_entry(connect_busses) 227 pci_dev4_inta = X86IntelMPIOIntAssignment( 228 interrupt_type = 'INT', 229 polarity = 'ConformPolarity', 230 trigger = 'ConformTrigger', 231 source_bus_id = 1, 232 source_bus_irq = 0 + (4 << 2), 233 dest_io_apic_id = io_apic.id, 234 dest_io_apic_intin = 16) 235 self.intel_mp_table.add_entry(pci_dev4_inta); |
234 assign_8259_0_to_apic = X86IntelMPIOIntAssignment( 235 interrupt_type = 'ExtInt', 236 polarity = 'ConformPolarity', 237 trigger = 'ConformTrigger', 238 source_bus_id = 0, 239 source_bus_irq = 0, 240 dest_io_apic_id = io_apic.id, 241 dest_io_apic_intin = 0) 242 self.intel_mp_table.add_entry(assign_8259_0_to_apic) 243 assign_0_to_apic = X86IntelMPIOIntAssignment( 244 interrupt_type = 'INT', 245 polarity = 'ConformPolarity', 246 trigger = 'ConformTrigger', 247 source_bus_id = 0, 248 source_bus_irq = 0, 249 dest_io_apic_id = io_apic.id, 250 dest_io_apic_intin = 2) 251 self.intel_mp_table.add_entry(assign_0_to_apic) 252 assign_8259_1_to_apic = X86IntelMPIOIntAssignment( 253 interrupt_type = 'ExtInt', 254 polarity = 'ConformPolarity', 255 trigger = 'ConformTrigger', 256 source_bus_id = 0, 257 source_bus_irq = 1, 258 dest_io_apic_id = io_apic.id, 259 dest_io_apic_intin = 0) 260 self.intel_mp_table.add_entry(assign_8259_1_to_apic) 261 assign_1_to_apic = X86IntelMPIOIntAssignment( 262 interrupt_type = 'INT', 263 polarity = 'ConformPolarity', 264 trigger = 'ConformTrigger', 265 source_bus_id = 0, 266 source_bus_irq = 1, 267 dest_io_apic_id = io_apic.id, 268 dest_io_apic_intin = 1) 269 self.intel_mp_table.add_entry(assign_1_to_apic) 270 assign_8259_4_to_apic = X86IntelMPIOIntAssignment( 271 interrupt_type = 'ExtInt', 272 polarity = 'ConformPolarity', 273 trigger = 'ConformTrigger', 274 source_bus_id = 0, 275 source_bus_irq = 4, 276 dest_io_apic_id = io_apic.id, 277 dest_io_apic_intin = 0) 278 self.intel_mp_table.add_entry(assign_8259_4_to_apic) 279 assign_4_to_apic = X86IntelMPIOIntAssignment( 280 interrupt_type = 'INT', 281 polarity = 'ConformPolarity', 282 trigger = 'ConformTrigger', 283 source_bus_id = 0, 284 source_bus_irq = 4, 285 dest_io_apic_id = io_apic.id, 286 dest_io_apic_intin = 4) 287 self.intel_mp_table.add_entry(assign_4_to_apic) 288 assign_8259_12_to_apic = X86IntelMPIOIntAssignment( 289 interrupt_type = 'ExtInt', 290 polarity = 'ConformPolarity', 291 trigger = 'ConformTrigger', 292 source_bus_id = 0, 293 source_bus_irq = 12, 294 dest_io_apic_id = io_apic.id, 295 dest_io_apic_intin = 0) 296 self.intel_mp_table.add_entry(assign_8259_12_to_apic) 297 assign_12_to_apic = X86IntelMPIOIntAssignment( 298 interrupt_type = 'INT', 299 polarity = 'ConformPolarity', 300 trigger = 'ConformTrigger', 301 source_bus_id = 0, 302 source_bus_irq = 12, 303 dest_io_apic_id = io_apic.id, 304 dest_io_apic_intin = 12) 305 self.intel_mp_table.add_entry(assign_12_to_apic) 306 assign_8259_14_to_apic = X86IntelMPIOIntAssignment( 307 interrupt_type = 'ExtInt', 308 polarity = 'ConformPolarity', 309 trigger = 'ConformTrigger', 310 source_bus_id = 0, 311 source_bus_irq = 14, 312 dest_io_apic_id = io_apic.id, 313 dest_io_apic_intin = 0) 314 self.intel_mp_table.add_entry(assign_8259_14_to_apic) 315 assign_14_to_apic = X86IntelMPIOIntAssignment( 316 interrupt_type = 'INT', 317 polarity = 'ConformPolarity', 318 trigger = 'ConformTrigger', 319 source_bus_id = 0, 320 source_bus_irq = 14, 321 dest_io_apic_id = io_apic.id, 322 dest_io_apic_intin = 14) 323 self.intel_mp_table.add_entry(assign_14_to_apic) | 236 def assignISAInt(irq, apicPin): 237 assign_8259_to_apic = X86IntelMPIOIntAssignment( 238 interrupt_type = 'ExtInt', 239 polarity = 'ConformPolarity', 240 trigger = 'ConformTrigger', 241 source_bus_id = 0, 242 source_bus_irq = irq, 243 dest_io_apic_id = io_apic.id, 244 dest_io_apic_intin = 0) 245 self.intel_mp_table.add_entry(assign_8259_to_apic) 246 assign_to_apic = X86IntelMPIOIntAssignment( 247 interrupt_type = 'INT', 248 polarity = 'ConformPolarity', 249 trigger = 'ConformTrigger', 250 source_bus_id = 0, 251 source_bus_irq = irq, 252 dest_io_apic_id = io_apic.id, 253 dest_io_apic_intin = apicPin) 254 self.intel_mp_table.add_entry(assign_to_apic) 255 assignISAInt(0, 2) 256 assignISAInt(1, 1) 257 for i in range(3, 15): 258 assignISAInt(i, i) |
324 325 | 259 260 |
326def makeLinuxX86System(mem_mode, mdesc = None): | 261def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None): |
327 self = LinuxX86System() 328 329 # Build up a generic x86 system and then specialize it for Linux | 262 self = LinuxX86System() 263 264 # Build up a generic x86 system and then specialize it for Linux |
330 makeX86System(mem_mode, mdesc, self) | 265 makeX86System(mem_mode, numCPUs, mdesc, self) |
331 332 # We assume below that there's at least 1MB of memory. We'll require 2 333 # just to avoid corner cases. 334 assert(self.physmem.range.second >= 0x200000) 335 336 # Mark the first megabyte of memory as reserved 337 self.e820_table.entries.append(X86E820Entry( 338 addr = 0, --- 98 unchanged lines hidden --- | 266 267 # We assume below that there's at least 1MB of memory. We'll require 2 268 # just to avoid corner cases. 269 assert(self.physmem.range.second >= 0x200000) 270 271 # Mark the first megabyte of memory as reserved 272 self.e820_table.entries.append(X86E820Entry( 273 addr = 0, --- 98 unchanged lines hidden --- |