FSConfig.py (6074:76c2b55fce6d) FSConfig.py (6122:9af6fb59752f)
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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33
34class CowIdeDisk(IdeDisk):
35 image = CowDiskImage(child=RawDiskImage(read_only=True),
36 read_only=False)
37
38 def childImage(self, ci):
39 self.image.child.image_file = ci
40
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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33
34class CowIdeDisk(IdeDisk):
35 image = CowDiskImage(child=RawDiskImage(read_only=True),
36 read_only=False)
37
38 def childImage(self, ci):
39 self.image.child.image_file = ci
40
41class MemBus(Bus):
42 badaddr_responder = BadAddr()
43 default = Self.badaddr_responder.pio
44
45
41def makeLinuxAlphaSystem(mem_mode, mdesc = None):
42 class BaseTsunami(Tsunami):
43 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
44 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
45 pci_func=0, pci_dev=0, pci_bus=0)
46
47 self = LinuxAlphaSystem()
48 if not mdesc:
49 # generic system
50 mdesc = SysConfig()
51 self.readfile = mdesc.script()
52 self.iobus = Bus(bus_id=0)
46def makeLinuxAlphaSystem(mem_mode, mdesc = None):
47 class BaseTsunami(Tsunami):
48 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
49 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
50 pci_func=0, pci_dev=0, pci_bus=0)
51
52 self = LinuxAlphaSystem()
53 if not mdesc:
54 # generic system
55 mdesc = SysConfig()
56 self.readfile = mdesc.script()
57 self.iobus = Bus(bus_id=0)
53 self.membus = Bus(bus_id=1)
58 self.membus = MemBus(bus_id=1)
54 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
55 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
56 self.bridge.side_a = self.iobus.port
57 self.bridge.side_b = self.membus.port
58 self.physmem.port = self.membus.port
59 self.disk0 = CowIdeDisk(driveID='master')
60 self.disk2 = CowIdeDisk(driveID='master')
61 self.disk0.childImage(mdesc.disk())

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85 self.image.child.image_file = ci
86
87 self = SparcSystem()
88 if not mdesc:
89 # generic system
90 mdesc = SysConfig()
91 self.readfile = mdesc.script()
92 self.iobus = Bus(bus_id=0)
59 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
60 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
61 self.bridge.side_a = self.iobus.port
62 self.bridge.side_b = self.membus.port
63 self.physmem.port = self.membus.port
64 self.disk0 = CowIdeDisk(driveID='master')
65 self.disk2 = CowIdeDisk(driveID='master')
66 self.disk0.childImage(mdesc.disk())

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90 self.image.child.image_file = ci
91
92 self = SparcSystem()
93 if not mdesc:
94 # generic system
95 mdesc = SysConfig()
96 self.readfile = mdesc.script()
97 self.iobus = Bus(bus_id=0)
93 self.membus = Bus(bus_id=1)
98 self.membus = MemBus(bus_id=1)
94 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
95 self.t1000 = T1000()
96 self.t1000.attachOnChipIO(self.membus)
97 self.t1000.attachIO(self.iobus)
98 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
99 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
100 self.bridge.side_a = self.iobus.port
101 self.bridge.side_b = self.membus.port

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125 pci_func=0, pci_dev=0, pci_bus=0)
126
127 self = LinuxMipsSystem()
128 if not mdesc:
129 # generic system
130 mdesc = SysConfig()
131 self.readfile = mdesc.script()
132 self.iobus = Bus(bus_id=0)
99 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
100 self.t1000 = T1000()
101 self.t1000.attachOnChipIO(self.membus)
102 self.t1000.attachIO(self.iobus)
103 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
104 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
105 self.bridge.side_a = self.iobus.port
106 self.bridge.side_b = self.membus.port

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130 pci_func=0, pci_dev=0, pci_bus=0)
131
132 self = LinuxMipsSystem()
133 if not mdesc:
134 # generic system
135 mdesc = SysConfig()
136 self.readfile = mdesc.script()
137 self.iobus = Bus(bus_id=0)
133 self.membus = Bus(bus_id=1)
138 self.membus = MemBus(bus_id=1)
134 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
135 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
136 self.bridge.side_a = self.iobus.port
137 self.bridge.side_b = self.membus.port
138 self.physmem.port = self.membus.port
139 self.disk0 = CowIdeDisk(driveID='master')
140 self.disk2 = CowIdeDisk(driveID='master')
141 self.disk0.childImage(mdesc.disk())

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165
166 if not mdesc:
167 # generic system
168 mdesc = SysConfig()
169 mdesc.diskname = 'x86root.img'
170 self.readfile = mdesc.script()
171
172 # Physical memory
139 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
140 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
141 self.bridge.side_a = self.iobus.port
142 self.bridge.side_b = self.membus.port
143 self.physmem.port = self.membus.port
144 self.disk0 = CowIdeDisk(driveID='master')
145 self.disk2 = CowIdeDisk(driveID='master')
146 self.disk0.childImage(mdesc.disk())

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170
171 if not mdesc:
172 # generic system
173 mdesc = SysConfig()
174 mdesc.diskname = 'x86root.img'
175 self.readfile = mdesc.script()
176
177 # Physical memory
173 self.membus = Bus(bus_id=1)
178 self.membus = MemBus(bus_id=1)
174 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
175 self.physmem.port = self.membus.port
176
177 # North Bridge
178 self.iobus = Bus(bus_id=0)
179 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
180 self.bridge.side_a = self.iobus.port
181 self.bridge.side_b = self.membus.port

--- 250 unchanged lines hidden --- 		179 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
180 self.physmem.port = self.membus.port
181
182 # North Bridge
183 self.iobus = Bus(bus_id=0)
184 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
185 self.bridge.side_a = self.iobus.port
186 self.bridge.side_b = self.membus.port

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