FSConfig.py (5840:6481e40d21eb) FSConfig.py (5841:08c65e29e57e)
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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161
162def makeX86System(mem_mode, mdesc = None, self = None):
163 if self == None:
164 self = X86System()
165
166 if not mdesc:
167 # generic system
168 mdesc = SysConfig()
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 152 unchanged lines hidden (view full) ---

161
162def makeX86System(mem_mode, mdesc = None, self = None):
163 if self == None:
164 self = X86System()
165
166 if not mdesc:
167 # generic system
168 mdesc = SysConfig()
169 mdesc.diskname = 'x86root.img'
169 self.readfile = mdesc.script()
170
171 # Physical memory
172 self.membus = Bus(bus_id=1)
173 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
174 self.physmem.port = self.membus.port
175
176 # North Bridge
177 self.iobus = Bus(bus_id=0)
178 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
179 self.bridge.side_a = self.iobus.port
180 self.bridge.side_b = self.membus.port
181
182 # Platform
183 self.pc = Pc()
184 self.pc.attachIO(self.iobus)
185
186 self.intrctrl = IntrControl()
187
170 self.readfile = mdesc.script()
171
172 # Physical memory
173 self.membus = Bus(bus_id=1)
174 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
175 self.physmem.port = self.membus.port
176
177 # North Bridge
178 self.iobus = Bus(bus_id=0)
179 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
180 self.bridge.side_a = self.iobus.port
181 self.bridge.side_b = self.membus.port
182
183 # Platform
184 self.pc = Pc()
185 self.pc.attachIO(self.iobus)
186
187 self.intrctrl = IntrControl()
188
189 # Disks
190 disk0 = CowIdeDisk(driveID='master')
191 disk2 = CowIdeDisk(driveID='master')
192 disk0.childImage(mdesc.disk())
193 disk2.childImage(disk('linux-bigswap2.img'))
194 self.pc.south_bridge.ide.disks = [disk0, disk2]
195
188 # Add in a Bios information structure.
189 structures = [X86SMBiosBiosInformation()]
190 self.smbios_table.structures = structures
191
192 # Set up the Intel MP table
193 bp = X86IntelMPProcessor(
194 local_apic_id = 0,
195 local_apic_version = 0x14,

--- 177 unchanged lines hidden --- 		196 # Add in a Bios information structure.
197 structures = [X86SMBiosBiosInformation()]
198 self.smbios_table.structures = structures
199
200 # Set up the Intel MP table
201 bp = X86IntelMPProcessor(
202 local_apic_id = 0,
203 local_apic_version = 0x14,

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