FSConfig.py (5411:d517a2f5f2a6) | FSConfig.py (5412:771996f1d68e) |
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1# Copyright (c) 2006-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 154 unchanged lines hidden (view full) --- 163 self = LinuxX86System() 164 if not mdesc: 165 # generic system 166 mdesc = SysConfig() 167 self.readfile = mdesc.script() 168 169 # Physical memory 170 self.membus = Bus(bus_id=1) | 1# Copyright (c) 2006-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 154 unchanged lines hidden (view full) --- 163 self = LinuxX86System() 164 if not mdesc: 165 # generic system 166 mdesc = SysConfig() 167 self.readfile = mdesc.script() 168 169 # Physical memory 170 self.membus = Bus(bus_id=1) |
171 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) | 171 self.physmem = PhysicalMemory(range = AddrRange('4GB')) #range = AddrRange(mdesc.mem())) |
172 self.physmem.port = self.membus.port 173 174 # North Bridge 175 self.iobus = Bus(bus_id=0) 176 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 177 self.bridge.side_a = self.iobus.port 178 self.bridge.side_b = self.membus.port 179 --- 95 unchanged lines hidden --- | 172 self.physmem.port = self.membus.port 173 174 # North Bridge 175 self.iobus = Bus(bus_id=0) 176 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 177 self.bridge.side_a = self.iobus.port 178 self.bridge.side_b = self.membus.port 179 --- 95 unchanged lines hidden --- |