FSConfig.py (4103:785279436bdd) FSConfig.py (4104:10b99ef0a7ff)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 82 unchanged lines hidden (view full) ---

91 if not mdesc:
92 # generic system
93 mdesc = SysConfig()
94 self.readfile = mdesc.script()
95 self.iobus = Bus(bus_id=0)
96 self.membus = Bus(bus_id=1)
97 self.bridge = Bridge()
98 self.t1000 = T1000()
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 82 unchanged lines hidden (view full) ---

91 if not mdesc:
92 # generic system
93 mdesc = SysConfig()
94 self.readfile = mdesc.script()
95 self.iobus = Bus(bus_id=0)
96 self.membus = Bus(bus_id=1)
97 self.bridge = Bridge()
98 self.t1000 = T1000()
99 self.t1000.attachOnChipIO(self.membus)
99 self.t1000.attachIO(self.iobus)
100 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
101 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
102 self.bridge.side_a = self.iobus.port
103 self.bridge.side_b = self.membus.port
104 self.physmem.port = self.membus.port
105 self.physmem2.port = self.membus.port
106 self.rom.port = self.membus.port

--- 29 unchanged lines hidden --- 		100 self.t1000.attachIO(self.iobus)
101 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
102 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
103 self.bridge.side_a = self.iobus.port
104 self.bridge.side_b = self.membus.port
105 self.physmem.port = self.membus.port
106 self.physmem2.port = self.membus.port
107 self.rom.port = self.membus.port

--- 29 unchanged lines hidden ---