FSConfig.py (3823:1c8f87aa103e) FSConfig.py (3898:42a529d97cf2)
1# Copyright (c) 2006 The Regents of The University of Michigan
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the

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33
34class CowIdeDisk(IdeDisk):
35 image = CowDiskImage(child=RawDiskImage(read_only=True),
36 read_only=False)
37
38 def childImage(self, ci):
39 self.image.child.image_file = ci
40
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the

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33
34class CowIdeDisk(IdeDisk):
35 image = CowDiskImage(child=RawDiskImage(read_only=True),
36 read_only=False)
37
38 def childImage(self, ci):
39 self.image.child.image_file = ci
40
41class CowMmDisk(MmDisk):
42 image = CowDiskImage(child=RawDiskImage(read_only=True),
43 read_only=False)
44
45 def childImage(self, ci):
46 self.image.child.image_file = ci
47
48
41class BaseTsunami(Tsunami):
42 ethernet = NSGigE(configdata=NSGigEPciData(),
43 pci_bus=0, pci_dev=1, pci_func=0)
44 etherint = NSGigEInt(device=Parent.ethernet)
45 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
46 pci_func=0, pci_dev=0, pci_bus=0)
47
48def makeLinuxAlphaSystem(mem_mode, mdesc = None):

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95 self.bridge.side_b = self.membus.port
96 self.physmem.port = self.membus.port
97 self.physmem2.port = self.membus.port
98 self.rom.port = self.membus.port
99 self.nvram.port = self.membus.port
100 self.hypervisor_desc.port = self.membus.port
101 self.partition_desc.port = self.membus.port
102 self.intrctrl = IntrControl()
49class BaseTsunami(Tsunami):
50 ethernet = NSGigE(configdata=NSGigEPciData(),
51 pci_bus=0, pci_dev=1, pci_func=0)
52 etherint = NSGigEInt(device=Parent.ethernet)
53 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
54 pci_func=0, pci_dev=0, pci_bus=0)
55
56def makeLinuxAlphaSystem(mem_mode, mdesc = None):

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103 self.bridge.side_b = self.membus.port
104 self.physmem.port = self.membus.port
105 self.physmem2.port = self.membus.port
106 self.rom.port = self.membus.port
107 self.nvram.port = self.membus.port
108 self.hypervisor_desc.port = self.membus.port
109 self.partition_desc.port = self.membus.port
110 self.intrctrl = IntrControl()
103 self.mem_mode = mem_mode
104
111 self.disk0 = CowMmDisk()
112 self.disk0.childImage(disk('disk.s10hw2'))
113 self.disk0.pio = self.iobus.port
105 self.reset_bin = binary('reset.bin')
106 self.hypervisor_bin = binary('q.bin')
107 self.openboot_bin = binary('openboot.bin')
108 self.nvram_bin = binary('nvram1')
109 self.hypervisor_desc_bin = binary('1up-hv.bin')
110 self.partition_desc_bin = binary('1up-md.bin')
111
112 return self

--- 14 unchanged lines hidden --- 		114 self.reset_bin = binary('reset.bin')
115 self.hypervisor_bin = binary('q.bin')
116 self.openboot_bin = binary('openboot.bin')
117 self.nvram_bin = binary('nvram1')
118 self.hypervisor_desc_bin = binary('1up-hv.bin')
119 self.partition_desc_bin = binary('1up-md.bin')
120
121 return self

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