FSConfig.py (3812:eaa215123a26) FSConfig.py (3814:33bd4ec9d66a)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 75 unchanged lines hidden (view full) ---

84 # generic system
85 mdesc = SysConfig()
86 self.readfile = mdesc.script()
87 self.iobus = Bus(bus_id=0)
88 self.membus = Bus(bus_id=1)
89 self.bridge = Bridge()
90 self.t1000 = T1000()
91 self.t1000.attachIO(self.iobus)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 75 unchanged lines hidden (view full) ---

84 # generic system
85 mdesc = SysConfig()
86 self.readfile = mdesc.script()
87 self.iobus = Bus(bus_id=0)
88 self.membus = Bus(bus_id=1)
89 self.bridge = Bridge()
90 self.t1000 = T1000()
91 self.t1000.attachIO(self.iobus)
92 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
92 self.physmem = PhysicalMemory(range = AddrRange('64MB'), zero = True)
93 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
93 self.bridge.side_a = self.iobus.port
94 self.bridge.side_b = self.membus.port
95 self.physmem.port = self.membus.port
94 self.bridge.side_a = self.iobus.port
95 self.bridge.side_b = self.membus.port
96 self.physmem.port = self.membus.port
97 self.physmem2.port = self.membus.port
96 self.rom.port = self.membus.port
97 self.nvram.port = self.membus.port
98 self.hypervisor_desc.port = self.membus.port
99 self.partition_desc.port = self.membus.port
100 self.intrctrl = IntrControl()
101 self.mem_mode = mem_mode
102
103 self.reset_bin = binary('reset.bin')

--- 21 unchanged lines hidden --- 		98 self.rom.port = self.membus.port
99 self.nvram.port = self.membus.port
100 self.hypervisor_desc.port = self.membus.port
101 self.partition_desc.port = self.membus.port
102 self.intrctrl = IntrControl()
103 self.mem_mode = mem_mode
104
105 self.reset_bin = binary('reset.bin')

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