FSConfig.py (3584:8c3cdb2c001c) FSConfig.py (3743:2061715f68d1)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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79 return self
80
81def makeSparcSystem(mem_mode, mdesc = None):
82 self = SparcSystem()
83 if not mdesc:
84 # generic system
85 mdesc = SysConfig()
86 self.readfile = mdesc.script()
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 70 unchanged lines hidden (view full) ---

79 return self
80
81def makeSparcSystem(mem_mode, mdesc = None):
82 self = SparcSystem()
83 if not mdesc:
84 # generic system
85 mdesc = SysConfig()
86 self.readfile = mdesc.script()
87 self.iobus = Bus(bus_id=0)
87 self.membus = Bus(bus_id=1)
88 self.membus = Bus(bus_id=1)
89 self.bridge = Bridge()
90 self.t1000 = T1000()
91 self.t1000.attachIO(self.iobus)
88 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
92 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
93 self.bridge.side_a = self.iobus.port
94 self.bridge.side_b = self.membus.port
89 self.physmem.port = self.membus.port
90 self.rom.port = self.membus.port
91 self.intrctrl = IntrControl()
92 self.mem_mode = mem_mode
93 self.kernel = binary('vmlinux')
94
95 self.reset_bin = binary('reset.bin')
96 self.hypervisor_bin = binary('q.bin')

--- 17 unchanged lines hidden --- 		95 self.physmem.port = self.membus.port
96 self.rom.port = self.membus.port
97 self.intrctrl = IntrControl()
98 self.mem_mode = mem_mode
99 self.kernel = binary('vmlinux')
100
101 self.reset_bin = binary('reset.bin')
102 self.hypervisor_bin = binary('q.bin')

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