FSConfig.py (3223:a2b6fa575c05) FSConfig.py (3304:c5917aeb8e2f)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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44 etherint = NSGigEInt(device=Parent.ethernet)
45 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
46 pci_func=0, pci_dev=0, pci_bus=0)
47
48def makeLinuxAlphaSystem(mem_mode, mdesc = None):
49 self = LinuxAlphaSystem()
50 if not mdesc:
51 # generic system
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 35 unchanged lines hidden (view full) ---

44 etherint = NSGigEInt(device=Parent.ethernet)
45 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
46 pci_func=0, pci_dev=0, pci_bus=0)
47
48def makeLinuxAlphaSystem(mem_mode, mdesc = None):
49 self = LinuxAlphaSystem()
50 if not mdesc:
51 # generic system
52 mdesc = Machine()
52 mdesc = SysConfig()
53 self.readfile = mdesc.script()
54 self.iobus = Bus(bus_id=0)
55 self.membus = Bus(bus_id=1)
56 self.bridge = Bridge()
57 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
58 self.bridge.side_a = self.iobus.port
59 self.bridge.side_b = self.membus.port
60 self.physmem.port = self.membus.port

--- 32 unchanged lines hidden --- 		53 self.readfile = mdesc.script()
54 self.iobus = Bus(bus_id=0)
55 self.membus = Bus(bus_id=1)
56 self.bridge = Bridge()
57 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
58 self.bridge.side_a = self.iobus.port
59 self.bridge.side_b = self.membus.port
60 self.physmem.port = self.membus.port

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