FSConfig.py (2995:34553e4fd1ac) | FSConfig.py (2998:1d5ea4e433f5) |
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1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Kevin Lim 28 29import m5 30from m5 import makeList 31from m5.objects import * 32from Benchmarks import * 33from FullO3Config import * | 1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Kevin Lim 28 29import m5 30from m5 import makeList 31from m5.objects import * 32from Benchmarks import * 33from FullO3Config import * |
34from Util import * | |
35 36class CowIdeDisk(IdeDisk): 37 image = CowDiskImage(child=RawDiskImage(read_only=True), 38 read_only=False) 39 40 def childImage(self, ci): 41 self.image.child.image_file = ci 42 43class BaseTsunami(Tsunami): 44 ethernet = NSGigE(configdata=NSGigEPciData(), 45 pci_bus=0, pci_dev=1, pci_func=0) 46 etherint = NSGigEInt(device=Parent.ethernet) 47 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 48 pci_func=0, pci_dev=0, pci_bus=0) 49 | 34 35class CowIdeDisk(IdeDisk): 36 image = CowDiskImage(child=RawDiskImage(read_only=True), 37 read_only=False) 38 39 def childImage(self, ci): 40 self.image.child.image_file = ci 41 42class BaseTsunami(Tsunami): 43 ethernet = NSGigE(configdata=NSGigEPciData(), 44 pci_bus=0, pci_dev=1, pci_func=0) 45 etherint = NSGigEInt(device=Parent.ethernet) 46 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 47 pci_func=0, pci_dev=0, pci_bus=0) 48 |
50def makeLinuxAlphaSystem(cpu, mem_mode, mdesc, icache=None, dcache=None, l2cache=None): | 49def makeLinuxAlphaSystem(mem_mode, mdesc): |
51 self = LinuxAlphaSystem() 52 self.readfile = mdesc.script() 53 self.iobus = Bus(bus_id=0) 54 self.membus = Bus(bus_id=1) 55 self.bridge = Bridge() 56 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 57 self.bridge.side_a = self.iobus.port 58 self.bridge.side_b = self.membus.port --- 8 unchanged lines hidden (view full) --- 67 self.tsunami.ide.dma = self.iobus.port 68 self.tsunami.ide.config = self.iobus.port 69 self.tsunami.ethernet.pio = self.iobus.port 70 self.tsunami.ethernet.dma = self.iobus.port 71 self.tsunami.ethernet.config = self.iobus.port 72 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 73 read_only = True)) 74 self.intrctrl = IntrControl() | 50 self = LinuxAlphaSystem() 51 self.readfile = mdesc.script() 52 self.iobus = Bus(bus_id=0) 53 self.membus = Bus(bus_id=1) 54 self.bridge = Bridge() 55 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 56 self.bridge.side_a = self.iobus.port 57 self.bridge.side_b = self.membus.port --- 8 unchanged lines hidden (view full) --- 66 self.tsunami.ide.dma = self.iobus.port 67 self.tsunami.ide.config = self.iobus.port 68 self.tsunami.ethernet.pio = self.iobus.port 69 self.tsunami.ethernet.dma = self.iobus.port 70 self.tsunami.ethernet.config = self.iobus.port 71 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 72 read_only = True)) 73 self.intrctrl = IntrControl() |
75 self.cpu = cpu | |
76 self.mem_mode = mem_mode | 74 self.mem_mode = mem_mode |
77 connectCpu(self.cpu, self.membus, icache, dcache, l2cache) 78 for each_cpu in makeList(self.cpu): 79 each_cpu.itb = AlphaITB() 80 each_cpu.dtb = AlphaDTB() 81 self.cpu.clock = '2GHz' | |
82 self.sim_console = SimConsole(listener=ConsoleListener(port=3456)) 83 self.kernel = binary('vmlinux') 84 self.pal = binary('ts_osfpal') 85 self.console = binary('console') 86 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 87 88 return self 89 90def makeDualRoot(testSystem, driveSystem): 91 self = Root() 92 self.testsys = testSystem 93 self.drivesys = driveSystem 94 95 self.etherdump = EtherDump(file='ethertrace') 96 self.etherlink = EtherLink(int1 = Parent.testsys.tsunami.etherint[0], 97 int2 = Parent.drivesys.tsunami.etherint[0], 98 dump = Parent.etherdump) 99 self.clock = '1THz' 100 return self | 75 self.sim_console = SimConsole(listener=ConsoleListener(port=3456)) 76 self.kernel = binary('vmlinux') 77 self.pal = binary('ts_osfpal') 78 self.console = binary('console') 79 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 80 81 return self 82 83def makeDualRoot(testSystem, driveSystem): 84 self = Root() 85 self.testsys = testSystem 86 self.drivesys = driveSystem 87 88 self.etherdump = EtherDump(file='ethertrace') 89 self.etherlink = EtherLink(int1 = Parent.testsys.tsunami.etherint[0], 90 int2 = Parent.drivesys.tsunami.etherint[0], 91 dump = Parent.etherdump) 92 self.clock = '1THz' 93 return self |