FSConfig.py (2953:10e7700b27f6) FSConfig.py (2969:d2f8f9a23082)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29import m5
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29import m5
30from m5 import makeList
30from m5.objects import *
31from FullO3Config import *
32from SysPaths import *
33from Util import *
34
35script.dir = '/z/saidi/work/m5.newmem/configs/boot'
36linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
37

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44
45class BaseTsunami(Tsunami):
46 ethernet = NSGigE(configdata=NSGigEPciData(),
47 pci_bus=0, pci_dev=1, pci_func=0)
48 etherint = NSGigEInt(device=Parent.ethernet)
49 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
50 pci_func=0, pci_dev=0, pci_bus=0)
51
31from m5.objects import *
32from FullO3Config import *
33from SysPaths import *
34from Util import *
35
36script.dir = '/z/saidi/work/m5.newmem/configs/boot'
37linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
38

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45
46class BaseTsunami(Tsunami):
47 ethernet = NSGigE(configdata=NSGigEPciData(),
48 pci_bus=0, pci_dev=1, pci_func=0)
49 etherint = NSGigEInt(device=Parent.ethernet)
50 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
51 pci_func=0, pci_dev=0, pci_bus=0)
52
52def MyLinuxAlphaSystem(cpu, mem_mode, linux_image, icache=None, dcache=None, l2cache=None):
53def makeLinuxAlphaSystem(cpu, mem_mode, linux_image, icache=None, dcache=None, l2cache=None):
53 self = LinuxAlphaSystem()
54 self.iobus = Bus(bus_id=0)
55 self.membus = Bus(bus_id=1)
56 self.bridge = Bridge()
57 self.physmem = PhysicalMemory(range = AddrRange('128MB'))
58 self.bridge.side_a = self.iobus.port
59 self.bridge.side_b = self.membus.port
60 self.physmem.port = self.membus.port

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71 self.tsunami.ethernet.dma = self.iobus.port
72 self.tsunami.ethernet.config = self.iobus.port
73 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
74 read_only = True))
75 self.intrctrl = IntrControl()
76 self.cpu = cpu
77 self.mem_mode = mem_mode
78 connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
54 self = LinuxAlphaSystem()
55 self.iobus = Bus(bus_id=0)
56 self.membus = Bus(bus_id=1)
57 self.bridge = Bridge()
58 self.physmem = PhysicalMemory(range = AddrRange('128MB'))
59 self.bridge.side_a = self.iobus.port
60 self.bridge.side_b = self.membus.port
61 self.physmem.port = self.membus.port

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72 self.tsunami.ethernet.dma = self.iobus.port
73 self.tsunami.ethernet.config = self.iobus.port
74 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
75 read_only = True))
76 self.intrctrl = IntrControl()
77 self.cpu = cpu
78 self.mem_mode = mem_mode
79 connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
79 for each_cpu in listWrapper(self.cpu):
80 for each_cpu in makeList(self.cpu):
80 each_cpu.itb = AlphaITB()
81 each_cpu.dtb = AlphaDTB()
82 self.cpu.clock = '2GHz'
83 self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
84 self.kernel = binary('vmlinux')
85 self.pal = binary('ts_osfpal')
86 self.console = binary('console')
87 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
88
89 return self
90
81 each_cpu.itb = AlphaITB()
82 each_cpu.dtb = AlphaDTB()
83 self.cpu.clock = '2GHz'
84 self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
85 self.kernel = binary('vmlinux')
86 self.pal = binary('ts_osfpal')
87 self.console = binary('console')
88 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
89
90 return self
91
91class TsunamiRoot(Root):
92 pass
93
94def DualRoot(clientSystem, serverSystem):
92def makeDualRoot(clientSystem, serverSystem):
95 self = Root()
96 self.client = clientSystem
97 self.server = serverSystem
98
99 self.etherdump = EtherDump(file='ethertrace')
100 self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
101 int2 = Parent.server.tsunami.etherint[0],
102 dump = Parent.etherdump)
103 self.clock = '1THz'
104 return self
93 self = Root()
94 self.client = clientSystem
95 self.server = serverSystem
96
97 self.etherdump = EtherDump(file='ethertrace')
98 self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
99 int2 = Parent.server.tsunami.etherint[0],
100 dump = Parent.etherdump)
101 self.clock = '1THz'
102 return self