FSConfig.py (2934:0b091d7d00f0) FSConfig.py (2953:10e7700b27f6)
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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69 self.tsunami.ide.config = self.iobus.port
70 self.tsunami.ethernet.pio = self.iobus.port
71 self.tsunami.ethernet.dma = self.iobus.port
72 self.tsunami.ethernet.config = self.iobus.port
73 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
74 read_only = True))
75 self.intrctrl = IntrControl()
76 self.cpu = cpu
1# Copyright (c) 2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 60 unchanged lines hidden (view full) ---

69 self.tsunami.ide.config = self.iobus.port
70 self.tsunami.ethernet.pio = self.iobus.port
71 self.tsunami.ethernet.dma = self.iobus.port
72 self.tsunami.ethernet.config = self.iobus.port
73 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = linux_image,
74 read_only = True))
75 self.intrctrl = IntrControl()
76 self.cpu = cpu
77
77 self.mem_mode = mem_mode
78 connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
79 for each_cpu in listWrapper(self.cpu):
80 each_cpu.itb = AlphaITB()
81 each_cpu.dtb = AlphaDTB()
82 self.cpu.clock = '2GHz'
83 self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
84 self.kernel = binary('vmlinux')
85 self.pal = binary('ts_osfpal')

--- 19 unchanged lines hidden --- 		78 connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
79 for each_cpu in listWrapper(self.cpu):
80 each_cpu.itb = AlphaITB()
81 each_cpu.dtb = AlphaDTB()
82 self.cpu.clock = '2GHz'
83 self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
84 self.kernel = binary('vmlinux')
85 self.pal = binary('ts_osfpal')

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