| FSConfig.py (10437:caec4a7b8b74) | FSConfig.py (10438:08fa6ad59594) |
|---|---|
| 1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 334 unchanged lines hidden (view full) --- 343 344 x86_sys.membus = MemBus() 345 346 # North Bridge 347 x86_sys.iobus = NoncoherentXBar() 348 x86_sys.bridge = Bridge(delay='50ns') 349 x86_sys.bridge.master = x86_sys.iobus.slave 350 x86_sys.bridge.slave = x86_sys.membus.master | 1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 334 unchanged lines hidden (view full) --- 343 344 x86_sys.membus = MemBus() 345 346 # North Bridge 347 x86_sys.iobus = NoncoherentXBar() 348 x86_sys.bridge = Bridge(delay='50ns') 349 x86_sys.bridge.master = x86_sys.iobus.slave 350 x86_sys.bridge.slave = x86_sys.membus.master |
| 351 # Allow the bridge to pass through the IO APIC (two pages), 352 # everything in the IO address range up to the local APIC, and 353 # then the entire PCI address space and beyond | 351 # Allow the bridge to pass through: 352 # 1) kernel configured PCI device memory map address: address range 353 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 354 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 355 # 3) everything in the IO address range up to the local APIC, and 356 # 4) then the entire PCI address space and beyond. |
| 354 x86_sys.bridge.ranges = \ 355 [ | 357 x86_sys.bridge.ranges = \ 358 [ |
| 356 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 357 x86_sys.pc.south_bridge.io_apic.pio_addr + 358 APIC_range_size - 1), | 359 AddrRange(0xC0000000, 0xFFFF0000), |
| 359 AddrRange(IO_address_space_base, 360 interrupts_address_space_base - 1), 361 AddrRange(pci_config_address_space_base, 362 Addr.max) 363 ] 364 365 # Create a bridge from the IO bus to the memory bus to allow access to 366 # the local APIC (two pages) --- 149 unchanged lines hidden (view full) --- 516 [ 517 # Mark the first megabyte of memory as reserved 518 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 519 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 520 # Mark the rest of physical memory as available 521 X86E820Entry(addr = 0x100000, 522 size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 523 range_type = 1), | 360 AddrRange(IO_address_space_base, 361 interrupts_address_space_base - 1), 362 AddrRange(pci_config_address_space_base, 363 Addr.max) 364 ] 365 366 # Create a bridge from the IO bus to the memory bus to allow access to 367 # the local APIC (two pages) --- 149 unchanged lines hidden (view full) --- 517 [ 518 # Mark the first megabyte of memory as reserved 519 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 520 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 521 # Mark the rest of physical memory as available 522 X86E820Entry(addr = 0x100000, 523 size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 524 range_type = 1), |
| 524 # Reserve the last 16kB of the 32-bit address space for the 525 # m5op interface 526 X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2), | |
| 527 ] 528 | 525 ] 526 |
| 527 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 528 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 529 # specific range can pass though bridge to iobus. 530 if len(self.mem_ranges) == 1: 531 entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 532 size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 533 range_type=2)) 534 535 # Reserve the last 16kB of the 32-bit address space for the m5op interface 536 entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 537 |
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| 529 # In case the physical memory is greater than 3GB, we split it into two 530 # parts and add a separate e820 entry for the second part. This entry 531 # starts at 0x100000000, which is the first address after the space 532 # reserved for devices. 533 if len(self.mem_ranges) == 2: 534 entries.append(X86E820Entry(addr = 0x100000000, 535 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 536 --- 29 unchanged lines hidden --- | 538 # In case the physical memory is greater than 3GB, we split it into two 539 # parts and add a separate e820 entry for the second part. This entry 540 # starts at 0x100000000, which is the first address after the space 541 # reserved for devices. 542 if len(self.mem_ranges) == 2: 543 entries.append(X86E820Entry(addr = 0x100000000, 544 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 545 --- 29 unchanged lines hidden --- |