FSConfig.py (10071:6234ea863e76) FSConfig.py (10118:5e1f04b4d5e4)
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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50 def childImage(self, ci):
51 self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 41 unchanged lines hidden (view full) ---

50 def childImage(self, ci):
51 self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
59 IO_address_space_base = 0x80000000000
58def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False):
59
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70 self.iobus = NoncoherentBus()
71 self.membus = MemBus()
72 # By default the bridge responds to all addresses above the I/O
73 # base address (including the PCI config space)
74 self.bridge = Bridge(delay='50ns',
75 ranges = [AddrRange(IO_address_space_base, Addr.max)])
76 self.mem_ranges = [AddrRange(mdesc.mem())]
77 self.bridge.master = self.iobus.slave
78 self.bridge.slave = self.membus.master
79 self.disk0 = CowIdeDisk(driveID='master')
80 self.disk2 = CowIdeDisk(driveID='master')
81 self.disk0.childImage(mdesc.disk())
82 self.disk2.childImage(disk('linux-bigswap2.img'))
70
83 self.tsunami = BaseTsunami()
71 self.tsunami = BaseTsunami()
72
73 # Create the io bus to connect all device ports
74 self.iobus = NoncoherentBus()
84 self.tsunami.attachIO(self.iobus)
75 self.tsunami.attachIO(self.iobus)
76
85 self.tsunami.ide.pio = self.iobus.master
86 self.tsunami.ide.config = self.iobus.master
77 self.tsunami.ide.pio = self.iobus.master
78 self.tsunami.ide.config = self.iobus.master
87 self.tsunami.ide.dma = self.iobus.slave
79
88 self.tsunami.ethernet.pio = self.iobus.master
89 self.tsunami.ethernet.config = self.iobus.master
80 self.tsunami.ethernet.pio = self.iobus.master
81 self.tsunami.ethernet.config = self.iobus.master
90 self.tsunami.ethernet.dma = self.iobus.slave
91 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
92 read_only = True))
93 self.intrctrl = IntrControl()
94 self.mem_mode = mem_mode
95 self.terminal = Terminal()
96 self.kernel = binary('vmlinux')
97 self.pal = binary('ts_osfpal')
98 self.console = binary('console')
99 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
100
82
101 self.system_port = self.membus.slave
83 if ruby:
84 # Store the dma devices for later connection to dma ruby ports.
85 # Append an underscore to dma_ports to avoid the SimObjectVector check.
86 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
87 else:
88 self.membus = MemBus()
102
89
103 return self
90 # By default the bridge responds to all addresses above the I/O
91 # base address (including the PCI config space)
92 IO_address_space_base = 0x80000000000
93 self.bridge = Bridge(delay='50ns',
94 ranges = [AddrRange(IO_address_space_base, Addr.max)])
95 self.bridge.master = self.iobus.slave
96 self.bridge.slave = self.membus.master
104
97
105def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
106 class BaseTsunami(Tsunami):
107 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
108 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
109 pci_func=0, pci_dev=0, pci_bus=0)
110 self = LinuxAlphaSystem()
111 self.mem_ranges = [AddrRange(mdesc.mem())]
112 if not mdesc:
113 # generic system
114 mdesc = SysConfig()
115 self.readfile = mdesc.script()
98 self.tsunami.ide.dma = self.iobus.slave
99 self.tsunami.ethernet.dma = self.iobus.slave
116
100
117 # Create pio bus to connect all device pio ports to rubymem's pio port
118 self.piobus = NoncoherentBus()
101 self.system_port = self.membus.slave
119
102
103 self.mem_ranges = [AddrRange(mdesc.mem())]
120 self.disk0 = CowIdeDisk(driveID='master')
121 self.disk2 = CowIdeDisk(driveID='master')
122 self.disk0.childImage(mdesc.disk())
123 self.disk2.childImage(disk('linux-bigswap2.img'))
104 self.disk0 = CowIdeDisk(driveID='master')
105 self.disk2 = CowIdeDisk(driveID='master')
106 self.disk0.childImage(mdesc.disk())
107 self.disk2.childImage(disk('linux-bigswap2.img'))
124 self.tsunami = BaseTsunami()
125 self.tsunami.attachIO(self.piobus)
126 self.tsunami.ide.pio = self.piobus.master
127 self.tsunami.ide.config = self.piobus.master
128 self.tsunami.ethernet.pio = self.piobus.master
129 self.tsunami.ethernet.config = self.piobus.master
130
131 #
132 # Store the dma devices for later connection to dma ruby ports.
133 # Append an underscore to dma_devices to avoid the SimObjectVector check.
134 #
135 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
136
137 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
138 read_only = True))
139 self.intrctrl = IntrControl()
140 self.mem_mode = mem_mode
141 self.terminal = Terminal()
142 self.kernel = binary('vmlinux')
143 self.pal = binary('ts_osfpal')
144 self.console = binary('console')

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387
388 # connect the io bus
389 x86_sys.pc.attachIO(x86_sys.iobus)
390
391 x86_sys.system_port = x86_sys.membus.slave
392
393def connectX86RubySystem(x86_sys):
394 # North Bridge
108 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
109 read_only = True))
110 self.intrctrl = IntrControl()
111 self.mem_mode = mem_mode
112 self.terminal = Terminal()
113 self.kernel = binary('vmlinux')
114 self.pal = binary('ts_osfpal')
115 self.console = binary('console')

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358
359 # connect the io bus
360 x86_sys.pc.attachIO(x86_sys.iobus)
361
362 x86_sys.system_port = x86_sys.membus.slave
363
364def connectX86RubySystem(x86_sys):
365 # North Bridge
395 x86_sys.piobus = NoncoherentBus()
366 x86_sys.iobus = NoncoherentBus()
396
397 # add the ide to the list of dma devices that later need to attach to
398 # dma controllers
399 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
367
368 # add the ide to the list of dma devices that later need to attach to
369 # dma controllers
370 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
400 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
371 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
401
402
403def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
404 Ruby = False):
405 if self == None:
406 self = X86System()
407
408 if not mdesc:

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373
374def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
375 Ruby = False):
376 if self == None:
377 self = X86System()
378
379 if not mdesc:

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