1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import convert
45
46class CowIdeDisk(IdeDisk):
47 image = CowDiskImage(child=RawDiskImage(read_only=True),
48 read_only=False)
49
50 def childImage(self, ci):
51 self.image.child.image_file = ci
52
53class MemBus(Bus):
54 badaddr_responder = BadAddr()
55 default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
59 IO_address_space_base = 0x80000000000
60 class BaseTsunami(Tsunami):
61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63 pci_func=0, pci_dev=0, pci_bus=0)
64
65 self = LinuxAlphaSystem()
66 if not mdesc:
67 # generic system
68 mdesc = SysConfig()
69 self.readfile = mdesc.script()
70 self.iobus = Bus(bus_id=0)
71 self.membus = MemBus(bus_id=1)
72 # By default the bridge responds to all addresses above the I/O
73 # base address (including the PCI config space)
74 self.bridge = Bridge(delay='50ns', nack_delay='4ns',
75 ranges = [AddrRange(IO_address_space_base, Addr.max)])
76 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
77 self.bridge.master = self.iobus.slave
78 self.bridge.slave = self.membus.master
79 self.physmem.port = self.membus.master
80 self.disk0 = CowIdeDisk(driveID='master')
81 self.disk2 = CowIdeDisk(driveID='master')
82 self.disk0.childImage(mdesc.disk())
83 self.disk2.childImage(disk('linux-bigswap2.img'))
84 self.tsunami = BaseTsunami()
85 self.tsunami.attachIO(self.iobus)
86 self.tsunami.ide.pio = self.iobus.master
87 self.tsunami.ide.config = self.iobus.master
88 self.tsunami.ide.dma = self.iobus.slave
89 self.tsunami.ethernet.pio = self.iobus.master
90 self.tsunami.ethernet.config = self.iobus.master
91 self.tsunami.ethernet.dma = self.iobus.slave
92 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
93 read_only = True))
94 self.intrctrl = IntrControl()
95 self.mem_mode = mem_mode
96 self.terminal = Terminal()
97 self.kernel = binary('vmlinux')
98 self.pal = binary('ts_osfpal')
99 self.console = binary('console')
100 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
101
102 self.system_port = self.membus.slave
103
104 return self
105
106def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
107 class BaseTsunami(Tsunami):
108 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
109 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
110 pci_func=0, pci_dev=0, pci_bus=0)
111
112 physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
113 self = LinuxAlphaSystem(physmem = physmem)
114 if not mdesc:
115 # generic system
116 mdesc = SysConfig()
117 self.readfile = mdesc.script()
118
119 # Create pio bus to connect all device pio ports to rubymem's pio port
120 self.piobus = Bus(bus_id=0)
121
122 #
123 # Pio functional accesses from devices need direct access to memory
124 # RubyPort currently does support functional accesses. Therefore provide
125 # the piobus a direct connection to physical memory
126 #
127 self.piobus.master = physmem.port
128
129 self.disk0 = CowIdeDisk(driveID='master')
130 self.disk2 = CowIdeDisk(driveID='master')
131 self.disk0.childImage(mdesc.disk())
132 self.disk2.childImage(disk('linux-bigswap2.img'))
133 self.tsunami = BaseTsunami()
134 self.tsunami.attachIO(self.piobus)
135 self.tsunami.ide.pio = self.piobus.master
136 self.tsunami.ide.config = self.piobus.master
|
137 self.tsunami.ide.dma = self.piobus.slave
|
137 self.tsunami.ethernet.pio = self.piobus.master
138 self.tsunami.ethernet.config = self.piobus.master
|
140 self.tsunami.ethernet.dma = self.piobus.slave
|
139
140 #
141 # Store the dma devices for later connection to dma ruby ports.
142 # Append an underscore to dma_devices to avoid the SimObjectVector check.
143 #
|
146 self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
|
| 144 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] |
145
146 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
147 read_only = True))
148 self.intrctrl = IntrControl()
149 self.mem_mode = mem_mode
150 self.terminal = Terminal()
151 self.kernel = binary('vmlinux')
152 self.pal = binary('ts_osfpal')
153 self.console = binary('console')
154 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
155
156 return self
157
158def makeSparcSystem(mem_mode, mdesc = None):
159 # Constants from iob.cc and uart8250.cc
160 iob_man_addr = 0x9800000000
161 uart_pio_size = 8
162
163 class CowMmDisk(MmDisk):
164 image = CowDiskImage(child=RawDiskImage(read_only=True),
165 read_only=False)
166
167 def childImage(self, ci):
168 self.image.child.image_file = ci
169
170 self = SparcSystem()
171 if not mdesc:
172 # generic system
173 mdesc = SysConfig()
174 self.readfile = mdesc.script()
175 self.iobus = Bus(bus_id=0)
176 self.membus = MemBus(bus_id=1)
177 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
178 self.t1000 = T1000()
179 self.t1000.attachOnChipIO(self.membus)
180 self.t1000.attachIO(self.iobus)
181 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
182 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
183 self.bridge.master = self.iobus.slave
184 self.bridge.slave = self.membus.master
185 self.physmem.port = self.membus.master
186 self.physmem2.port = self.membus.master
187 self.rom.port = self.membus.master
188 self.nvram.port = self.membus.master
189 self.hypervisor_desc.port = self.membus.master
190 self.partition_desc.port = self.membus.master
191 self.intrctrl = IntrControl()
192 self.disk0 = CowMmDisk()
193 self.disk0.childImage(disk('disk.s10hw2'))
194 self.disk0.pio = self.iobus.master
195
196 # The puart0 and hvuart are placed on the IO bus, so create ranges
197 # for them. The remaining IO range is rather fragmented, so poke
198 # holes for the iob and partition descriptors etc.
199 self.bridge.ranges = \
200 [
201 AddrRange(self.t1000.puart0.pio_addr,
202 self.t1000.puart0.pio_addr + uart_pio_size - 1),
203 AddrRange(self.disk0.pio_addr,
204 self.t1000.fake_jbi.pio_addr +
205 self.t1000.fake_jbi.pio_size - 1),
206 AddrRange(self.t1000.fake_clk.pio_addr,
207 iob_man_addr - 1),
208 AddrRange(self.t1000.fake_l2_1.pio_addr,
209 self.t1000.fake_ssi.pio_addr +
210 self.t1000.fake_ssi.pio_size - 1),
211 AddrRange(self.t1000.hvuart.pio_addr,
212 self.t1000.hvuart.pio_addr + uart_pio_size - 1)
213 ]
214 self.reset_bin = binary('reset_new.bin')
215 self.hypervisor_bin = binary('q_new.bin')
216 self.openboot_bin = binary('openboot_new.bin')
217 self.nvram_bin = binary('nvram1')
218 self.hypervisor_desc_bin = binary('1up-hv.bin')
219 self.partition_desc_bin = binary('1up-md.bin')
220
221 self.system_port = self.membus.slave
222
223 return self
224
225def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
226 assert machine_type
227
228 if bare_metal:
229 self = ArmSystem()
230 else:
231 self = LinuxArmSystem()
232
233 if not mdesc:
234 # generic system
235 mdesc = SysConfig()
236
237 self.readfile = mdesc.script()
238 self.iobus = Bus(bus_id=0)
239 self.membus = MemBus(bus_id=1)
240 self.membus.badaddr_responder.warn_access = "warn"
241 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
242 self.bridge.master = self.iobus.slave
243 self.bridge.slave = self.membus.master
244
245 self.mem_mode = mem_mode
246
247 if machine_type == "RealView_PBX":
248 self.realview = RealViewPBX()
249 elif machine_type == "RealView_EB":
250 self.realview = RealViewEB()
251 elif machine_type == "VExpress_ELT":
252 self.realview = VExpress_ELT()
253 elif machine_type == "VExpress_EMM":
254 self.realview = VExpress_EMM()
255 self.load_addr_mask = 0xffffffff
256 else:
257 print "Unknown Machine Type"
258 sys.exit(1)
259
260 self.cf0 = CowIdeDisk(driveID='master')
261 self.cf0.childImage(mdesc.disk())
262 # default to an IDE controller rather than a CF one
263 # assuming we've got one
264 try:
265 self.realview.ide.disks = [self.cf0]
266 except:
267 self.realview.cf_ctrl.disks = [self.cf0]
268
269 if bare_metal:
270 # EOT character on UART will end the simulation
271 self.realview.uart.end_on_eot = True
272 self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
273 zero = True)
274 else:
275 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
276 self.machine_type = machine_type
277 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
278 print "The currently selected ARM platforms doesn't support"
279 print " the amount of DRAM you've selected. Please try"
280 print " another platform"
281 sys.exit(1)
282
283 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
284 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
285
286 self.physmem = PhysicalMemory(range = AddrRange(self.realview.mem_start_addr,
287 size = mdesc.mem()))
288 self.realview.setupBootLoader(self.membus, self, binary)
289 self.gic_cpu_addr = self.realview.gic.cpu_addr
290 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
291
292 if mdesc.disk().lower().count('android'):
293 boot_flags += " init=/init "
294 self.boot_osflags = boot_flags
295
296 self.physmem.port = self.membus.master
297 self.realview.attachOnChipIO(self.membus, self.bridge)
298 self.realview.attachIO(self.iobus)
299 self.intrctrl = IntrControl()
300 self.terminal = Terminal()
301 self.vncserver = VncServer()
302
303 self.system_port = self.membus.slave
304
305 return self
306
307
308def makeLinuxMipsSystem(mem_mode, mdesc = None):
309 class BaseMalta(Malta):
310 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
311 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
312 pci_func=0, pci_dev=0, pci_bus=0)
313
314 self = LinuxMipsSystem()
315 if not mdesc:
316 # generic system
317 mdesc = SysConfig()
318 self.readfile = mdesc.script()
319 self.iobus = Bus(bus_id=0)
320 self.membus = MemBus(bus_id=1)
321 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
322 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
323 self.bridge.master = self.iobus.slave
324 self.bridge.slave = self.membus.master
325 self.physmem.port = self.membus.master
326 self.disk0 = CowIdeDisk(driveID='master')
327 self.disk2 = CowIdeDisk(driveID='master')
328 self.disk0.childImage(mdesc.disk())
329 self.disk2.childImage(disk('linux-bigswap2.img'))
330 self.malta = BaseMalta()
331 self.malta.attachIO(self.iobus)
332 self.malta.ide.pio = self.iobus.master
333 self.malta.ide.config = self.iobus.master
334 self.malta.ide.dma = self.iobus.slave
335 self.malta.ethernet.pio = self.iobus.master
336 self.malta.ethernet.config = self.iobus.master
337 self.malta.ethernet.dma = self.iobus.slave
338 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
339 read_only = True))
340 self.intrctrl = IntrControl()
341 self.mem_mode = mem_mode
342 self.terminal = Terminal()
343 self.kernel = binary('mips/vmlinux')
344 self.console = binary('mips/console')
345 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
346
347 self.system_port = self.membus.slave
348
349 return self
350
351def x86IOAddress(port):
352 IO_address_space_base = 0x8000000000000000
353 return IO_address_space_base + port
354
355def connectX86ClassicSystem(x86_sys, numCPUs):
356 # Constants similar to x86_traits.hh
357 IO_address_space_base = 0x8000000000000000
358 pci_config_address_space_base = 0xc000000000000000
359 interrupts_address_space_base = 0xa000000000000000
360 APIC_range_size = 1 << 12;
361
362 x86_sys.membus = MemBus(bus_id=1)
363 x86_sys.physmem.port = x86_sys.membus.master
364
365 # North Bridge
366 x86_sys.iobus = Bus(bus_id=0)
367 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
368 x86_sys.bridge.master = x86_sys.iobus.slave
369 x86_sys.bridge.slave = x86_sys.membus.master
370 # Allow the bridge to pass through the IO APIC (two pages),
371 # everything in the IO address range up to the local APIC, and
372 # then the entire PCI address space and beyond
373 x86_sys.bridge.ranges = \
374 [
375 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
376 x86_sys.pc.south_bridge.io_apic.pio_addr +
377 APIC_range_size - 1),
378 AddrRange(IO_address_space_base,
379 interrupts_address_space_base - 1),
380 AddrRange(pci_config_address_space_base,
381 Addr.max)
382 ]
383
384 # Create a bridge from the IO bus to the memory bus to allow access to
385 # the local APIC (two pages)
386 x86_sys.apicbridge = Bridge(delay='50ns', nack_delay='4ns')
387 x86_sys.apicbridge.slave = x86_sys.iobus.master
388 x86_sys.apicbridge.master = x86_sys.membus.slave
389 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
390 interrupts_address_space_base +
391 numCPUs * APIC_range_size
392 - 1)]
393
394 # connect the io bus
395 x86_sys.pc.attachIO(x86_sys.iobus)
396
397 x86_sys.system_port = x86_sys.membus.slave
398
399def connectX86RubySystem(x86_sys):
400 # North Bridge
401 x86_sys.piobus = Bus(bus_id=0)
402
403 #
404 # Pio functional accesses from devices need direct access to memory
405 # RubyPort currently does support functional accesses. Therefore provide
406 # the piobus a direct connection to physical memory
407 #
408 x86_sys.piobus.master = x86_sys.physmem.port
|
409 # add the ide to the list of dma devices that later need to attach to
410 # dma controllers
411 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
412 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) |
413
|
412 x86_sys.pc.attachIO(x86_sys.piobus)
|
414
|
414
|
415def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
416 if self == None:
417 self = X86System()
418
419 if not mdesc:
420 # generic system
421 mdesc = SysConfig()
422 self.readfile = mdesc.script()
423
424 self.mem_mode = mem_mode
425
426 # Physical memory
427 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
428
429 # Platform
430 self.pc = Pc()
431
432 # Create and connect the busses required by each memory system
433 if Ruby:
434 connectX86RubySystem(self)
|
435 # add the ide to the list of dma devices that later need to attach to
436 # dma controllers
437 self._dma_devices = [self.pc.south_bridge.ide]
|
435 else:
436 connectX86ClassicSystem(self, numCPUs)
437
438 self.intrctrl = IntrControl()
439
440 # Disks
441 disk0 = CowIdeDisk(driveID='master')
442 disk2 = CowIdeDisk(driveID='master')
443 disk0.childImage(mdesc.disk())
444 disk2.childImage(disk('linux-bigswap2.img'))
445 self.pc.south_bridge.ide.disks = [disk0, disk2]
446
447 # Add in a Bios information structure.
448 structures = [X86SMBiosBiosInformation()]
449 self.smbios_table.structures = structures
450
451 # Set up the Intel MP table
452 base_entries = []
453 ext_entries = []
454 for i in xrange(numCPUs):
455 bp = X86IntelMPProcessor(
456 local_apic_id = i,
457 local_apic_version = 0x14,
458 enable = True,
459 bootstrap = (i == 0))
460 base_entries.append(bp)
461 io_apic = X86IntelMPIOAPIC(
462 id = numCPUs,
463 version = 0x11,
464 enable = True,
465 address = 0xfec00000)
466 self.pc.south_bridge.io_apic.apic_id = io_apic.id
467 base_entries.append(io_apic)
468 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
469 base_entries.append(isa_bus)
470 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
471 base_entries.append(pci_bus)
472 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
473 subtractive_decode=True, parent_bus=1)
474 ext_entries.append(connect_busses)
475 pci_dev4_inta = X86IntelMPIOIntAssignment(
476 interrupt_type = 'INT',
477 polarity = 'ConformPolarity',
478 trigger = 'ConformTrigger',
479 source_bus_id = 1,
480 source_bus_irq = 0 + (4 << 2),
481 dest_io_apic_id = io_apic.id,
482 dest_io_apic_intin = 16)
483 base_entries.append(pci_dev4_inta)
484 def assignISAInt(irq, apicPin):
485 assign_8259_to_apic = X86IntelMPIOIntAssignment(
486 interrupt_type = 'ExtInt',
487 polarity = 'ConformPolarity',
488 trigger = 'ConformTrigger',
489 source_bus_id = 0,
490 source_bus_irq = irq,
491 dest_io_apic_id = io_apic.id,
492 dest_io_apic_intin = 0)
493 base_entries.append(assign_8259_to_apic)
494 assign_to_apic = X86IntelMPIOIntAssignment(
495 interrupt_type = 'INT',
496 polarity = 'ConformPolarity',
497 trigger = 'ConformTrigger',
498 source_bus_id = 0,
499 source_bus_irq = irq,
500 dest_io_apic_id = io_apic.id,
501 dest_io_apic_intin = apicPin)
502 base_entries.append(assign_to_apic)
503 assignISAInt(0, 2)
504 assignISAInt(1, 1)
505 for i in range(3, 15):
506 assignISAInt(i, i)
507 self.intel_mp_table.base_entries = base_entries
508 self.intel_mp_table.ext_entries = ext_entries
509
510def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
511 self = LinuxX86System()
512
513 # Build up the x86 system and then specialize it for Linux
514 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
515
516 # We assume below that there's at least 1MB of memory. We'll require 2
517 # just to avoid corner cases.
518 assert(self.physmem.range.second.getValue() >= 0x200000)
519
520 self.e820_table.entries = \
521 [
522 # Mark the first megabyte of memory as reserved
523 X86E820Entry(addr = 0, size = '1MB', range_type = 2),
524 # Mark the rest as available
525 X86E820Entry(addr = 0x100000,
526 size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
527 range_type = 1)
528 ]
529
530 # Command line
531 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
532 'root=/dev/hda1'
533 return self
534
535
536def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
537 self = Root(full_system = full_system)
538 self.testsys = testSystem
539 self.drivesys = driveSystem
540 self.etherlink = EtherLink()
541 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
542 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
543
544 if hasattr(testSystem, 'realview'):
545 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
546 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
547 elif hasattr(testSystem, 'tsunami'):
548 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
549 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
550 else:
551 fatal("Don't know how to connect these system together")
552
553 if dumpfile:
554 self.etherdump = EtherDump(file=dumpfile)
555 self.etherlink.dump = Parent.etherdump
556
557 return self
558
559def setMipsOptions(TestCPUClass):
560 #CP0 Configuration
561 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
562 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
563 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
564 TestCPUClass.CoreParams.CP0_PRId_Revision = 0
565
566 #CP0 Interrupt Control
567 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
568 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
569
570 # Config Register
571 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
572 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
573 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
574 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
575 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
576 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
577 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
578
579 #Config 1 Register
580 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
581 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
582 # ***VERY IMPORTANT***
583 # Remember to modify CP0_Config1 according to cache specs
584 # Examine file ../common/Cache.py
585 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
586 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
587 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
588 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
589 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
590 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
591 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
592 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
593 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
594 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
595 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
596 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
597 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
598
599 #Config 2 Register
600 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
601 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
602 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
603 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
604 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
605 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
606 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
607 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
608 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
609
610
611 #Config 3 Register
612 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
613 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
614 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
615 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
616 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
617 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
618 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
619 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
620 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
621
622 #SRS Ctl - HSS
623 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
624
625
626 #TestCPUClass.CoreParams.tlb = TLB()
627 #TestCPUClass.CoreParams.UnifiedTLB = 1
|