1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44
45class CowIdeDisk(IdeDisk):
46 image = CowDiskImage(child=RawDiskImage(read_only=True),
47 read_only=False)
48
49 def childImage(self, ci):
50 self.image.child.image_file = ci
51
52class MemBus(Bus):
53 badaddr_responder = BadAddr()
54 default = Self.badaddr_responder.pio
55
56
57def makeLinuxAlphaSystem(mem_mode, mdesc = None):
58 class BaseTsunami(Tsunami):
59 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
60 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
61 pci_func=0, pci_dev=0, pci_bus=0)
62
63 self = LinuxAlphaSystem()
64 if not mdesc:
65 # generic system
66 mdesc = SysConfig()
67 self.readfile = mdesc.script()
68 self.iobus = Bus(bus_id=0)
69 self.membus = MemBus(bus_id=1)
70 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
71 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
72 self.bridge.side_a = self.iobus.port
73 self.bridge.side_b = self.membus.port
74 self.physmem.port = self.membus.port
75 self.disk0 = CowIdeDisk(driveID='master')
76 self.disk2 = CowIdeDisk(driveID='master')
77 self.disk0.childImage(mdesc.disk())
78 self.disk2.childImage(disk('linux-bigswap2.img'))
79 self.tsunami = BaseTsunami()
80 self.tsunami.attachIO(self.iobus)
81 self.tsunami.ide.pio = self.iobus.port
82 self.tsunami.ethernet.pio = self.iobus.port
83 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
84 read_only = True))
85 self.intrctrl = IntrControl()
86 self.mem_mode = mem_mode
87 self.terminal = Terminal()
88 self.kernel = binary('vmlinux')
89 self.pal = binary('ts_osfpal')
90 self.console = binary('console')
91 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
92
93 return self
94
95def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
96 class BaseTsunami(Tsunami):
97 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
98 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
99 pci_func=0, pci_dev=0, pci_bus=0)
100
101 physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
102 self = LinuxAlphaSystem(physmem = physmem)
103 if not mdesc:
104 # generic system
105 mdesc = SysConfig()
106 self.readfile = mdesc.script()
107
108 # Create pio bus to connect all device pio ports to rubymem's pio port
109 self.piobus = Bus(bus_id=0)
110
111 #
112 # Pio functional accesses from devices need direct access to memory
113 # RubyPort currently does support functional accesses. Therefore provide
114 # the piobus a direct connection to physical memory
115 #
116 self.piobus.port = physmem.port
117
118 self.disk0 = CowIdeDisk(driveID='master')
119 self.disk2 = CowIdeDisk(driveID='master')
120 self.disk0.childImage(mdesc.disk())
121 self.disk2.childImage(disk('linux-bigswap2.img'))
122 self.tsunami = BaseTsunami()
123 self.tsunami.attachIO(self.piobus)
124 self.tsunami.ide.pio = self.piobus.port
125 self.tsunami.ethernet.pio = self.piobus.port
126
127 #
128 # Store the dma devices for later connection to dma ruby ports.
129 # Append an underscore to dma_devices to avoid the SimObjectVector check.
130 #
131 self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
132
133 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
134 read_only = True))
135 self.intrctrl = IntrControl()
136 self.mem_mode = mem_mode
137 self.terminal = Terminal()
138 self.kernel = binary('vmlinux')
139 self.pal = binary('ts_osfpal')
140 self.console = binary('console')
141 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
142
143 return self
144
145def makeSparcSystem(mem_mode, mdesc = None):
146 class CowMmDisk(MmDisk):
147 image = CowDiskImage(child=RawDiskImage(read_only=True),
148 read_only=False)
149
150 def childImage(self, ci):
151 self.image.child.image_file = ci
152
153 self = SparcSystem()
154 if not mdesc:
155 # generic system
156 mdesc = SysConfig()
157 self.readfile = mdesc.script()
158 self.iobus = Bus(bus_id=0)
159 self.membus = MemBus(bus_id=1)
160 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
161 self.t1000 = T1000()
162 self.t1000.attachOnChipIO(self.membus)
163 self.t1000.attachIO(self.iobus)
164 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
165 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
166 self.bridge.side_a = self.iobus.port
167 self.bridge.side_b = self.membus.port
168 self.physmem.port = self.membus.port
169 self.physmem2.port = self.membus.port
170 self.rom.port = self.membus.port
171 self.nvram.port = self.membus.port
172 self.hypervisor_desc.port = self.membus.port
173 self.partition_desc.port = self.membus.port
174 self.intrctrl = IntrControl()
175 self.disk0 = CowMmDisk()
176 self.disk0.childImage(disk('disk.s10hw2'))
177 self.disk0.pio = self.iobus.port
178 self.reset_bin = binary('reset_new.bin')
179 self.hypervisor_bin = binary('q_new.bin')
180 self.openboot_bin = binary('openboot_new.bin')
181 self.nvram_bin = binary('nvram1')
182 self.hypervisor_desc_bin = binary('1up-hv.bin')
183 self.partition_desc_bin = binary('1up-md.bin')
184
185 return self
186
187def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
188 assert machine_type
189
190 if bare_metal:
191 self = ArmSystem()
192 else:
193 self = LinuxArmSystem()
194
195 if not mdesc:
196 # generic system
197 mdesc = SysConfig()
198
199 self.readfile = mdesc.script()
200 self.iobus = Bus(bus_id=0)
201 self.membus = MemBus(bus_id=1)
202 self.membus.badaddr_responder.warn_access = "warn"
203 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
204 self.bridge.side_a = self.iobus.port
205 self.bridge.side_b = self.membus.port
206
207 self.mem_mode = mem_mode
208
209 if machine_type == "RealView_PBX":
210 self.realview = RealViewPBX()
211 elif machine_type == "RealView_EB":
212 self.realview = RealViewEB()
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213 elif machine_type == "VersatileExpress":
214 self.realview = VExpress()
|
213 elif machine_type == "VExpress_ELT":
214 self.realview = VExpress_ELT() |
215 else:
216 print "Unknown Machine Type"
217 sys.exit(1)
218
219 use_cf = False
220 if mdesc.disk()[-4:] == ".img":
221 use_cf = True
222 self.cf0 = CowIdeDisk(driveID='master')
223 self.cf0.childImage(mdesc.disk())
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224 self.realview.cf_ctrl.disks = [self.cf0]
225
|
224 # default to an IDE controller rather than a CF one
225 # assuming we've got one
226 try:
227 self.realview.ide.disks = [self.cf0]
228 except:
229 self.realview.cf_ctrl.disks = [self.cf0] |
230 if bare_metal:
231 # EOT character on UART will end the simulation
232 self.realview.uart.end_on_eot = True
233 self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')),
234 zero = True)
235 else:
236 self.kernel = binary('vmlinux.arm')
237 self.machine_type = machine_type
238 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
239 'rw loglevel=8 '
240 if use_cf:
241 self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')),
242 zero = True)
243 boot_flags += "mem=256MB root=/dev/sda1 "
244 self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
245 size = '64MB'), zero = True)
246 self.nvmem.port = self.membus.port
247 self.boot_loader = binary('boot.arm')
248 self.boot_loader_mem = self.nvmem
249 self.gic_cpu_addr = self.realview.gic.cpu_addr
250 self.flags_addr = self.realview.realview_io.pio_addr + 0x30
251 else:
252 self.physmem = PhysicalMemory(range = AddrRange(Addr('128MB')),
253 zero = True)
254 self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'),
255 size = '128MB'),
256 file = disk(mdesc.disk()))
257 self.diskmem.port = self.membus.port
258 boot_flags += "mem=128MB slram=slram0,0x8000000,+0x8000000 " + \
259 "mtdparts=slram0:- root=/dev/mtdblock0 "
260
261 if mdesc.disk().count('android'):
262 boot_flags += "init=/init "
263 self.boot_osflags = boot_flags
264
265 self.physmem.port = self.membus.port
266 self.realview.attachOnChipIO(self.membus)
267 self.realview.attachIO(self.iobus)
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264
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268 self.intrctrl = IntrControl()
269 self.terminal = Terminal()
270 self.vncserver = VncServer()
271
272 return self
273
274
275def makeLinuxMipsSystem(mem_mode, mdesc = None):
276 class BaseMalta(Malta):
277 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
278 ide = IdeController(disks=[Parent.disk0, Parent.disk2],
279 pci_func=0, pci_dev=0, pci_bus=0)
280
281 self = LinuxMipsSystem()
282 if not mdesc:
283 # generic system
284 mdesc = SysConfig()
285 self.readfile = mdesc.script()
286 self.iobus = Bus(bus_id=0)
287 self.membus = MemBus(bus_id=1)
288 self.bridge = Bridge(delay='50ns', nack_delay='4ns')
289 self.physmem = PhysicalMemory(range = AddrRange('1GB'))
290 self.bridge.side_a = self.iobus.port
291 self.bridge.side_b = self.membus.port
292 self.physmem.port = self.membus.port
293 self.disk0 = CowIdeDisk(driveID='master')
294 self.disk2 = CowIdeDisk(driveID='master')
295 self.disk0.childImage(mdesc.disk())
296 self.disk2.childImage(disk('linux-bigswap2.img'))
297 self.malta = BaseMalta()
298 self.malta.attachIO(self.iobus)
299 self.malta.ide.pio = self.iobus.port
300 self.malta.ethernet.pio = self.iobus.port
301 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
302 read_only = True))
303 self.intrctrl = IntrControl()
304 self.mem_mode = mem_mode
305 self.terminal = Terminal()
306 self.kernel = binary('mips/vmlinux')
307 self.console = binary('mips/console')
308 self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
309
310 return self
311
312def x86IOAddress(port):
313 IO_address_space_base = 0x8000000000000000
314 return IO_address_space_base + port
315
316def connectX86ClassicSystem(x86_sys):
317 x86_sys.membus = MemBus(bus_id=1)
318 x86_sys.physmem.port = x86_sys.membus.port
319
320 # North Bridge
321 x86_sys.iobus = Bus(bus_id=0)
322 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
323 x86_sys.bridge.side_a = x86_sys.iobus.port
324 x86_sys.bridge.side_b = x86_sys.membus.port
325
326 # connect the io bus
327 x86_sys.pc.attachIO(x86_sys.iobus)
328
329def connectX86RubySystem(x86_sys):
330 # North Bridge
331 x86_sys.piobus = Bus(bus_id=0)
332
333 #
334 # Pio functional accesses from devices need direct access to memory
335 # RubyPort currently does support functional accesses. Therefore provide
336 # the piobus a direct connection to physical memory
337 #
338 x86_sys.piobus.port = x86_sys.physmem.port
339
340 x86_sys.pc.attachIO(x86_sys.piobus)
341
342
343def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
344 if self == None:
345 self = X86System()
346
347 if not mdesc:
348 # generic system
349 mdesc = SysConfig()
350 self.readfile = mdesc.script()
351
352 self.mem_mode = mem_mode
353
354 # Physical memory
355 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
356
357 # Platform
358 self.pc = Pc()
359
360 # Create and connect the busses required by each memory system
361 if Ruby:
362 connectX86RubySystem(self)
363 # add the ide to the list of dma devices that later need to attach to
364 # dma controllers
365 self._dma_devices = [self.pc.south_bridge.ide]
366 else:
367 connectX86ClassicSystem(self)
368
369 self.intrctrl = IntrControl()
370
371 # Disks
372 disk0 = CowIdeDisk(driveID='master')
373 disk2 = CowIdeDisk(driveID='master')
374 disk0.childImage(mdesc.disk())
375 disk2.childImage(disk('linux-bigswap2.img'))
376 self.pc.south_bridge.ide.disks = [disk0, disk2]
377
378 # Add in a Bios information structure.
379 structures = [X86SMBiosBiosInformation()]
380 self.smbios_table.structures = structures
381
382 # Set up the Intel MP table
383 base_entries = []
384 ext_entries = []
385 for i in xrange(numCPUs):
386 bp = X86IntelMPProcessor(
387 local_apic_id = i,
388 local_apic_version = 0x14,
389 enable = True,
390 bootstrap = (i == 0))
391 base_entries.append(bp)
392 io_apic = X86IntelMPIOAPIC(
393 id = numCPUs,
394 version = 0x11,
395 enable = True,
396 address = 0xfec00000)
397 self.pc.south_bridge.io_apic.apic_id = io_apic.id
398 base_entries.append(io_apic)
399 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
400 base_entries.append(isa_bus)
401 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
402 base_entries.append(pci_bus)
403 connect_busses = X86IntelMPBusHierarchy(bus_id=0,
404 subtractive_decode=True, parent_bus=1)
405 ext_entries.append(connect_busses)
406 pci_dev4_inta = X86IntelMPIOIntAssignment(
407 interrupt_type = 'INT',
408 polarity = 'ConformPolarity',
409 trigger = 'ConformTrigger',
410 source_bus_id = 1,
411 source_bus_irq = 0 + (4 << 2),
412 dest_io_apic_id = io_apic.id,
413 dest_io_apic_intin = 16)
414 base_entries.append(pci_dev4_inta)
415 def assignISAInt(irq, apicPin):
416 assign_8259_to_apic = X86IntelMPIOIntAssignment(
417 interrupt_type = 'ExtInt',
418 polarity = 'ConformPolarity',
419 trigger = 'ConformTrigger',
420 source_bus_id = 0,
421 source_bus_irq = irq,
422 dest_io_apic_id = io_apic.id,
423 dest_io_apic_intin = 0)
424 base_entries.append(assign_8259_to_apic)
425 assign_to_apic = X86IntelMPIOIntAssignment(
426 interrupt_type = 'INT',
427 polarity = 'ConformPolarity',
428 trigger = 'ConformTrigger',
429 source_bus_id = 0,
430 source_bus_irq = irq,
431 dest_io_apic_id = io_apic.id,
432 dest_io_apic_intin = apicPin)
433 base_entries.append(assign_to_apic)
434 assignISAInt(0, 2)
435 assignISAInt(1, 1)
436 for i in range(3, 15):
437 assignISAInt(i, i)
438 self.intel_mp_table.base_entries = base_entries
439 self.intel_mp_table.ext_entries = ext_entries
440
441def setWorkCountOptions(system, options):
442 if options.work_item_id != None:
443 system.work_item_id = options.work_item_id
444 if options.work_begin_cpu_id_exit != None:
445 system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
446 if options.work_end_exit_count != None:
447 system.work_end_exit_count = options.work_end_exit_count
448 if options.work_end_checkpoint_count != None:
449 system.work_end_ckpt_count = options.work_end_checkpoint_count
450 if options.work_begin_exit_count != None:
451 system.work_begin_exit_count = options.work_begin_exit_count
452 if options.work_begin_checkpoint_count != None:
453 system.work_begin_ckpt_count = options.work_begin_checkpoint_count
454 if options.work_cpus_checkpoint_count != None:
455 system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
456
457
458def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
459 self = LinuxX86System()
460
461 # Build up the x86 system and then specialize it for Linux
462 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
463
464 # We assume below that there's at least 1MB of memory. We'll require 2
465 # just to avoid corner cases.
466 assert(self.physmem.range.second.getValue() >= 0x200000)
467
468 self.e820_table.entries = \
469 [
470 # Mark the first megabyte of memory as reserved
471 X86E820Entry(addr = 0, size = '1MB', range_type = 2),
472 # Mark the rest as available
473 X86E820Entry(addr = 0x100000,
474 size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
475 range_type = 1)
476 ]
477
478 # Command line
479 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
480 'root=/dev/hda1'
481 return self
482
483
484def makeDualRoot(testSystem, driveSystem, dumpfile):
485 self = Root()
486 self.testsys = testSystem
487 self.drivesys = driveSystem
488 self.etherlink = EtherLink()
489 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
490 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
491
492 if dumpfile:
493 self.etherdump = EtherDump(file=dumpfile)
494 self.etherlink.dump = Parent.etherdump
495
496 return self
497
498def setMipsOptions(TestCPUClass):
499 #CP0 Configuration
500 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
501 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
502 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
503 TestCPUClass.CoreParams.CP0_PRId_Revision = 0
504
505 #CP0 Interrupt Control
506 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
507 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
508
509 # Config Register
510 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
511 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
512 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
513 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
514 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
515 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
516 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
517
518 #Config 1 Register
519 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
520 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
521 # ***VERY IMPORTANT***
522 # Remember to modify CP0_Config1 according to cache specs
523 # Examine file ../common/Cache.py
524 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
525 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
526 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
527 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
528 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
529 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
530 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
531 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
532 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
533 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
534 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
535 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
536 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
537
538 #Config 2 Register
539 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
540 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
541 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
542 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
543 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
544 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
545 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
546 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
547 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
548
549
550 #Config 3 Register
551 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
552 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
553 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
554 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
555 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
556 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
557 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
558 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
559 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
560
561 #SRS Ctl - HSS
562 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
563
564
565 #TestCPUClass.CoreParams.tlb = TLB()
566 #TestCPUClass.CoreParams.UnifiedTLB = 1
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