1# Copyright (c) 2010 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 14# Copyright (c) 2006-2008 The Regents of The University of Michigan 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Kevin Lim 41 42from m5.objects import * 43from Benchmarks import * 44 45class CowIdeDisk(IdeDisk): 46 image = CowDiskImage(child=RawDiskImage(read_only=True), 47 read_only=False) 48 49 def childImage(self, ci): 50 self.image.child.image_file = ci 51 52class MemBus(Bus): 53 badaddr_responder = BadAddr() 54 default = Self.badaddr_responder.pio 55 56 57def makeLinuxAlphaSystem(mem_mode, mdesc = None): 58 class BaseTsunami(Tsunami): 59 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 60 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 61 pci_func=0, pci_dev=0, pci_bus=0) 62 63 self = LinuxAlphaSystem() 64 if not mdesc: 65 # generic system 66 mdesc = SysConfig() 67 self.readfile = mdesc.script() 68 self.iobus = Bus(bus_id=0) 69 self.membus = MemBus(bus_id=1) 70 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 71 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 72 self.bridge.side_a = self.iobus.port 73 self.bridge.side_b = self.membus.port 74 self.physmem.port = self.membus.port 75 self.disk0 = CowIdeDisk(driveID='master') 76 self.disk2 = CowIdeDisk(driveID='master') 77 self.disk0.childImage(mdesc.disk()) 78 self.disk2.childImage(disk('linux-bigswap2.img')) 79 self.tsunami = BaseTsunami() 80 self.tsunami.attachIO(self.iobus) 81 self.tsunami.ide.pio = self.iobus.port 82 self.tsunami.ethernet.pio = self.iobus.port 83 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 84 read_only = True)) 85 self.intrctrl = IntrControl() 86 self.mem_mode = mem_mode 87 self.terminal = Terminal() 88 self.kernel = binary('vmlinux') 89 self.pal = binary('ts_osfpal') 90 self.console = binary('console') 91 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 92 93 return self 94 95def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 96 class BaseTsunami(Tsunami): 97 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 98 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 99 pci_func=0, pci_dev=0, pci_bus=0) 100 101 physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 102 self = LinuxAlphaSystem(physmem = physmem) 103 if not mdesc: 104 # generic system 105 mdesc = SysConfig() 106 self.readfile = mdesc.script() 107 108 # Create pio bus to connect all device pio ports to rubymem's pio port 109 self.piobus = Bus(bus_id=0) 110 111 # 112 # Pio functional accesses from devices need direct access to memory 113 # RubyPort currently does support functional accesses. Therefore provide 114 # the piobus a direct connection to physical memory 115 # 116 self.piobus.port = physmem.port 117 118 self.disk0 = CowIdeDisk(driveID='master') 119 self.disk2 = CowIdeDisk(driveID='master') 120 self.disk0.childImage(mdesc.disk()) 121 self.disk2.childImage(disk('linux-bigswap2.img')) 122 self.tsunami = BaseTsunami() 123 self.tsunami.attachIO(self.piobus) 124 self.tsunami.ide.pio = self.piobus.port 125 self.tsunami.ethernet.pio = self.piobus.port 126 127 # 128 # Store the dma devices for later connection to dma ruby ports. 129 # Append an underscore to dma_devices to avoid the SimObjectVector check. 130 # 131 self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet] 132 133 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 134 read_only = True)) 135 self.intrctrl = IntrControl() 136 self.mem_mode = mem_mode 137 self.terminal = Terminal() 138 self.kernel = binary('vmlinux') 139 self.pal = binary('ts_osfpal') 140 self.console = binary('console') 141 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 142 143 return self 144 145def makeSparcSystem(mem_mode, mdesc = None): 146 class CowMmDisk(MmDisk): 147 image = CowDiskImage(child=RawDiskImage(read_only=True), 148 read_only=False) 149 150 def childImage(self, ci): 151 self.image.child.image_file = ci 152 153 self = SparcSystem() 154 if not mdesc: 155 # generic system 156 mdesc = SysConfig() 157 self.readfile = mdesc.script() 158 self.iobus = Bus(bus_id=0) 159 self.membus = MemBus(bus_id=1) 160 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 161 self.t1000 = T1000() 162 self.t1000.attachOnChipIO(self.membus) 163 self.t1000.attachIO(self.iobus) 164 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 165 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 166 self.bridge.side_a = self.iobus.port 167 self.bridge.side_b = self.membus.port 168 self.physmem.port = self.membus.port 169 self.physmem2.port = self.membus.port 170 self.rom.port = self.membus.port 171 self.nvram.port = self.membus.port 172 self.hypervisor_desc.port = self.membus.port 173 self.partition_desc.port = self.membus.port 174 self.intrctrl = IntrControl() 175 self.disk0 = CowMmDisk() 176 self.disk0.childImage(disk('disk.s10hw2')) 177 self.disk0.pio = self.iobus.port 178 self.reset_bin = binary('reset_new.bin') 179 self.hypervisor_bin = binary('q_new.bin') 180 self.openboot_bin = binary('openboot_new.bin') 181 self.nvram_bin = binary('nvram1') 182 self.hypervisor_desc_bin = binary('1up-hv.bin') 183 self.partition_desc_bin = binary('1up-md.bin') 184 185 return self 186 187def makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False, 188 machine_type = None): 189 if bare_metal: 190 self = ArmSystem() 191 else: 192 self = LinuxArmSystem() 193 194 if not mdesc: 195 # generic system 196 mdesc = SysConfig() 197 198 self.readfile = mdesc.script() 199 self.iobus = Bus(bus_id=0) 200 self.membus = MemBus(bus_id=1) 201 self.membus.badaddr_responder.warn_access = "warn" 202 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 203 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True) 204 self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'), 205 file = disk('ael-arm.ext2')) 206 self.bridge.side_a = self.iobus.port 207 self.bridge.side_b = self.membus.port 208 self.physmem.port = self.membus.port 209 self.diskmem.port = self.membus.port 210 211 self.mem_mode = mem_mode 212 213 #self.cf0 = CowIdeDisk(driveID='master') 214 #self.cf0.childImage(mdesc.disk()) 215 #self.cf_ctrl = IdeController(disks=[self.cf0], 216 # pci_func = 0, pci_dev = 0, pci_bus = 0, 217 # io_shift = 1, ctrl_offset = 2, Command = 0x1, 218 # BAR0 = 0x18000000, BAR0Size = '16B', 219 # BAR1 = 0x18000100, BAR1Size = '1B', 220 # BAR0LegacyIO = True, BAR1LegacyIO = True,) 221 #self.cf_ctrl.pio = self.iobus.port 222 223 if machine_type == "RealView_PBX": 224 self.realview = RealViewPBX() 225 elif machine_type == "RealView_EB": 226 self.realview = RealViewEB() 227 else: 228 print "Unknown Machine Type" 229 sys.exit(1) 230 231 if not bare_metal and machine_type: 232 self.machine_type = machine_type 233 elif bare_metal: 234 self.realview.uart.end_on_eot = True 235 236 self.realview.attachOnChipIO(self.membus) 237 self.realview.attachIO(self.iobus) 238 239 self.intrctrl = IntrControl() 240 self.terminal = Terminal() 241 self.kernel = binary('vmlinux.arm') 242 self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480' + \ 243 ' norandmaps slram=slram0,0x8000000,+0x8000000' + \ 244 ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0' 245 246 return self 247 248 249def makeLinuxMipsSystem(mem_mode, mdesc = None): 250 class BaseMalta(Malta): 251 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 252 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 253 pci_func=0, pci_dev=0, pci_bus=0) 254 255 self = LinuxMipsSystem() 256 if not mdesc: 257 # generic system 258 mdesc = SysConfig() 259 self.readfile = mdesc.script() 260 self.iobus = Bus(bus_id=0) 261 self.membus = MemBus(bus_id=1) 262 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 263 self.physmem = PhysicalMemory(range = AddrRange('1GB')) 264 self.bridge.side_a = self.iobus.port 265 self.bridge.side_b = self.membus.port 266 self.physmem.port = self.membus.port 267 self.disk0 = CowIdeDisk(driveID='master') 268 self.disk2 = CowIdeDisk(driveID='master') 269 self.disk0.childImage(mdesc.disk()) 270 self.disk2.childImage(disk('linux-bigswap2.img')) 271 self.malta = BaseMalta() 272 self.malta.attachIO(self.iobus) 273 self.malta.ide.pio = self.iobus.port 274 self.malta.ethernet.pio = self.iobus.port 275 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 276 read_only = True)) 277 self.intrctrl = IntrControl() 278 self.mem_mode = mem_mode 279 self.terminal = Terminal() 280 self.kernel = binary('mips/vmlinux') 281 self.console = binary('mips/console') 282 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 283 284 return self 285 286def x86IOAddress(port): 287 IO_address_space_base = 0x8000000000000000 288 return IO_address_space_base + port; 289 290def connectX86ClassicSystem(x86_sys): 291 x86_sys.membus = MemBus(bus_id=1) 292 x86_sys.physmem.port = x86_sys.membus.port 293 294 # North Bridge 295 x86_sys.iobus = Bus(bus_id=0) 296 x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') 297 x86_sys.bridge.side_a = x86_sys.iobus.port 298 x86_sys.bridge.side_b = x86_sys.membus.port 299 300 # connect the io bus 301 x86_sys.pc.attachIO(x86_sys.iobus) 302 303def connectX86RubySystem(x86_sys): 304 # North Bridge 305 x86_sys.piobus = Bus(bus_id=0) 306 307 # 308 # Pio functional accesses from devices need direct access to memory 309 # RubyPort currently does support functional accesses. Therefore provide 310 # the piobus a direct connection to physical memory 311 # 312 x86_sys.piobus.port = x86_sys.physmem.port 313 314 x86_sys.pc.attachIO(x86_sys.piobus) 315 316 317def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 318 if self == None: 319 self = X86System() 320 321 if not mdesc: 322 # generic system 323 mdesc = SysConfig() 324 self.readfile = mdesc.script() 325 326 self.mem_mode = mem_mode 327 328 # Physical memory 329 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 330 331 # Platform 332 self.pc = Pc() 333 334 # Create and connect the busses required by each memory system 335 if Ruby: 336 connectX86RubySystem(self)
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340 else: 341 connectX86ClassicSystem(self) 342 343 self.intrctrl = IntrControl() 344 345 # Disks 346 disk0 = CowIdeDisk(driveID='master') 347 disk2 = CowIdeDisk(driveID='master') 348 disk0.childImage(mdesc.disk()) 349 disk2.childImage(disk('linux-bigswap2.img')) 350 self.pc.south_bridge.ide.disks = [disk0, disk2] 351 352 # Add in a Bios information structure. 353 structures = [X86SMBiosBiosInformation()] 354 self.smbios_table.structures = structures 355 356 # Set up the Intel MP table 357 for i in xrange(numCPUs): 358 bp = X86IntelMPProcessor( 359 local_apic_id = i, 360 local_apic_version = 0x14, 361 enable = True, 362 bootstrap = (i == 0)) 363 self.intel_mp_table.add_entry(bp) 364 io_apic = X86IntelMPIOAPIC( 365 id = numCPUs, 366 version = 0x11, 367 enable = True, 368 address = 0xfec00000) 369 self.pc.south_bridge.io_apic.apic_id = io_apic.id 370 self.intel_mp_table.add_entry(io_apic) 371 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 372 self.intel_mp_table.add_entry(isa_bus) 373 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 374 self.intel_mp_table.add_entry(pci_bus) 375 connect_busses = X86IntelMPBusHierarchy(bus_id=0, 376 subtractive_decode=True, parent_bus=1) 377 self.intel_mp_table.add_entry(connect_busses) 378 pci_dev4_inta = X86IntelMPIOIntAssignment( 379 interrupt_type = 'INT', 380 polarity = 'ConformPolarity', 381 trigger = 'ConformTrigger', 382 source_bus_id = 1, 383 source_bus_irq = 0 + (4 << 2), 384 dest_io_apic_id = io_apic.id, 385 dest_io_apic_intin = 16) 386 self.intel_mp_table.add_entry(pci_dev4_inta); 387 def assignISAInt(irq, apicPin): 388 assign_8259_to_apic = X86IntelMPIOIntAssignment( 389 interrupt_type = 'ExtInt', 390 polarity = 'ConformPolarity', 391 trigger = 'ConformTrigger', 392 source_bus_id = 0, 393 source_bus_irq = irq, 394 dest_io_apic_id = io_apic.id, 395 dest_io_apic_intin = 0) 396 self.intel_mp_table.add_entry(assign_8259_to_apic) 397 assign_to_apic = X86IntelMPIOIntAssignment( 398 interrupt_type = 'INT', 399 polarity = 'ConformPolarity', 400 trigger = 'ConformTrigger', 401 source_bus_id = 0, 402 source_bus_irq = irq, 403 dest_io_apic_id = io_apic.id, 404 dest_io_apic_intin = apicPin) 405 self.intel_mp_table.add_entry(assign_to_apic) 406 assignISAInt(0, 2) 407 assignISAInt(1, 1) 408 for i in range(3, 15): 409 assignISAInt(i, i) 410 411def setWorkCountOptions(system, options): 412 if options.work_item_id != None: 413 system.work_item_id = options.work_item_id 414 if options.work_begin_cpu_id_exit != None: 415 system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 416 if options.work_end_exit_count != None: 417 system.work_end_exit_count = options.work_end_exit_count 418 if options.work_end_checkpoint_count != None: 419 system.work_end_ckpt_count = options.work_end_checkpoint_count 420 if options.work_begin_exit_count != None: 421 system.work_begin_exit_count = options.work_begin_exit_count 422 if options.work_begin_checkpoint_count != None: 423 system.work_begin_ckpt_count = options.work_begin_checkpoint_count 424 if options.work_cpus_checkpoint_count != None: 425 system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 426 427 428def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 429 self = LinuxX86System() 430 431 # Build up the x86 system and then specialize it for Linux 432 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 433 434 # We assume below that there's at least 1MB of memory. We'll require 2 435 # just to avoid corner cases. 436 assert(self.physmem.range.second.getValue() >= 0x200000) 437 438 # Mark the first megabyte of memory as reserved 439 self.e820_table.entries.append(X86E820Entry( 440 addr = 0, 441 size = '1MB', 442 range_type = 2)) 443 444 # Mark the rest as available 445 self.e820_table.entries.append(X86E820Entry( 446 addr = 0x100000, 447 size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 448 range_type = 1)) 449 450 # Command line 451 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 452 'root=/dev/hda1' 453 return self 454 455 456def makeDualRoot(testSystem, driveSystem, dumpfile): 457 self = Root() 458 self.testsys = testSystem 459 self.drivesys = driveSystem 460 self.etherlink = EtherLink() 461 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 462 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 463 464 if dumpfile: 465 self.etherdump = EtherDump(file=dumpfile) 466 self.etherlink.dump = Parent.etherdump 467 468 return self 469 470def setMipsOptions(TestCPUClass): 471 #CP0 Configuration 472 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 473 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 474 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 475 TestCPUClass.CoreParams.CP0_PRId_Revision = 0 476 477 #CP0 Interrupt Control 478 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 479 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 480 481 # Config Register 482 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 483 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 484 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 485 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 486 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 487 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 488 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 489 490 #Config 1 Register 491 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 492 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 493 # ***VERY IMPORTANT*** 494 # Remember to modify CP0_Config1 according to cache specs 495 # Examine file ../common/Cache.py 496 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 497 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 498 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 499 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 500 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 501 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 502 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 503 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 504 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 505 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 506 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 507 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 508 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 509 510 #Config 2 Register 511 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 512 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 513 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 514 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 515 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 516 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 517 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 518 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 519 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 520 521 522 #Config 3 Register 523 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 524 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 525 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 526 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 527 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 528 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 529 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 530 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 531 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 532 533 #SRS Ctl - HSS 534 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 535 536 537 #TestCPUClass.CoreParams.tlb = TLB() 538 #TestCPUClass.CoreParams.UnifiedTLB = 1
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