1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 41 unchanged lines hidden (view full) --- 50 def childImage(self, ci): 51 self.image.child.image_file = ci 52 53class MemBus(CoherentBus): 54 badaddr_responder = BadAddr() 55 default = Self.badaddr_responder.pio 56 57 |
58def makeLinuxAlphaSystem(mem_mode, mdesc = None): |
59 IO_address_space_base = 0x80000000000 60 class BaseTsunami(Tsunami): 61 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 62 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 63 pci_func=0, pci_dev=0, pci_bus=0) 64 65 self = LinuxAlphaSystem() 66 if not mdesc: 67 # generic system 68 mdesc = SysConfig() 69 self.readfile = mdesc.script() 70 self.iobus = NoncoherentBus() 71 self.membus = MemBus() 72 # By default the bridge responds to all addresses above the I/O 73 # base address (including the PCI config space) 74 self.bridge = Bridge(delay='50ns', 75 ranges = [AddrRange(IO_address_space_base, Addr.max)]) |
76 self.mem_ranges = [AddrRange(mdesc.mem())] |
77 self.bridge.master = self.iobus.slave 78 self.bridge.slave = self.membus.master |
79 self.disk0 = CowIdeDisk(driveID='master') 80 self.disk2 = CowIdeDisk(driveID='master') 81 self.disk0.childImage(mdesc.disk()) 82 self.disk2.childImage(disk('linux-bigswap2.img')) 83 self.tsunami = BaseTsunami() 84 self.tsunami.attachIO(self.iobus) 85 self.tsunami.ide.pio = self.iobus.master 86 self.tsunami.ide.config = self.iobus.master --- 10 unchanged lines hidden (view full) --- 97 self.pal = binary('ts_osfpal') 98 self.console = binary('console') 99 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 100 101 self.system_port = self.membus.slave 102 103 return self 104 |
105def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): |
106 class BaseTsunami(Tsunami): 107 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 108 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 109 pci_func=0, pci_dev=0, pci_bus=0) |
110 self = LinuxAlphaSystem() 111 self.mem_ranges = [AddrRange(mdesc.mem())] |
112 if not mdesc: 113 # generic system 114 mdesc = SysConfig() 115 self.readfile = mdesc.script() 116 117 # Create pio bus to connect all device pio ports to rubymem's pio port 118 self.piobus = NoncoherentBus() 119 |
120 self.disk0 = CowIdeDisk(driveID='master') 121 self.disk2 = CowIdeDisk(driveID='master') 122 self.disk0.childImage(mdesc.disk()) 123 self.disk2.childImage(disk('linux-bigswap2.img')) 124 self.tsunami = BaseTsunami() 125 self.tsunami.attachIO(self.piobus) 126 self.tsunami.ide.pio = self.piobus.master 127 self.tsunami.ide.config = self.piobus.master --- 13 unchanged lines hidden (view full) --- 141 self.terminal = Terminal() 142 self.kernel = binary('vmlinux') 143 self.pal = binary('ts_osfpal') 144 self.console = binary('console') 145 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 146 147 return self 148 |
149def makeSparcSystem(mem_mode, mdesc = None): |
150 # Constants from iob.cc and uart8250.cc 151 iob_man_addr = 0x9800000000 152 uart_pio_size = 8 153 154 class CowMmDisk(MmDisk): 155 image = CowDiskImage(child=RawDiskImage(read_only=True), 156 read_only=False) 157 --- 6 unchanged lines hidden (view full) --- 164 mdesc = SysConfig() 165 self.readfile = mdesc.script() 166 self.iobus = NoncoherentBus() 167 self.membus = MemBus() 168 self.bridge = Bridge(delay='50ns') 169 self.t1000 = T1000() 170 self.t1000.attachOnChipIO(self.membus) 171 self.t1000.attachIO(self.iobus) |
172 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 173 AddrRange(Addr('2GB'), size ='256MB')] |
174 self.bridge.master = self.iobus.slave 175 self.bridge.slave = self.membus.master |
176 self.rom.port = self.membus.master 177 self.nvram.port = self.membus.master 178 self.hypervisor_desc.port = self.membus.master 179 self.partition_desc.port = self.membus.master 180 self.intrctrl = IntrControl() 181 self.disk0 = CowMmDisk() 182 self.disk0.childImage(disk('disk.s10hw2')) 183 self.disk0.pio = self.iobus.master --- 22 unchanged lines hidden (view full) --- 206 self.nvram_bin = binary('nvram1') 207 self.hypervisor_desc_bin = binary('1up-hv.bin') 208 self.partition_desc_bin = binary('1up-md.bin') 209 210 self.system_port = self.membus.slave 211 212 return self 213 |
214def makeArmSystem(mem_mode, machine_type, mdesc = None, |
215 dtb_filename = None, bare_metal=False): 216 assert machine_type 217 218 if bare_metal: 219 self = ArmSystem() 220 else: 221 self = LinuxArmSystem() 222 --- 31 unchanged lines hidden (view full) --- 254 try: 255 self.realview.ide.disks = [self.cf0] 256 except: 257 self.realview.cf_ctrl.disks = [self.cf0] 258 259 if bare_metal: 260 # EOT character on UART will end the simulation 261 self.realview.uart.end_on_eot = True |
262 self.mem_ranges = [AddrRange(mdesc.mem())] |
263 else: 264 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 265 if dtb_filename is not None: 266 self.dtb_filename = dtb_filename 267 self.machine_type = machine_type 268 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 269 print "The currently selected ARM platforms doesn't support" 270 print " the amount of DRAM you've selected. Please try" 271 print " another platform" 272 sys.exit(1) 273 274 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 275 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() |
276 self.mem_ranges = [AddrRange(self.realview.mem_start_addr, 277 size = mdesc.mem())] |
278 self.realview.setupBootLoader(self.membus, self, binary) 279 self.gic_cpu_addr = self.realview.gic.cpu_addr 280 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 281 282 if mdesc.disk().lower().count('android'): 283 boot_flags += " init=/init " 284 self.boot_osflags = boot_flags |
285 self.realview.attachOnChipIO(self.membus, self.bridge) 286 self.realview.attachIO(self.iobus) 287 self.intrctrl = IntrControl() 288 self.terminal = Terminal() 289 self.vncserver = VncServer() 290 291 self.system_port = self.membus.slave 292 293 return self 294 295 |
296def makeLinuxMipsSystem(mem_mode, mdesc = None): |
297 class BaseMalta(Malta): 298 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 299 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 300 pci_func=0, pci_dev=0, pci_bus=0) 301 302 self = LinuxMipsSystem() 303 if not mdesc: 304 # generic system 305 mdesc = SysConfig() 306 self.readfile = mdesc.script() 307 self.iobus = NoncoherentBus() 308 self.membus = MemBus() 309 self.bridge = Bridge(delay='50ns') |
310 self.mem_ranges = [AddrRange('1GB')] |
311 self.bridge.master = self.iobus.slave 312 self.bridge.slave = self.membus.master |
313 self.disk0 = CowIdeDisk(driveID='master') 314 self.disk2 = CowIdeDisk(driveID='master') 315 self.disk0.childImage(mdesc.disk()) 316 self.disk2.childImage(disk('linux-bigswap2.img')) 317 self.malta = BaseMalta() 318 self.malta.attachIO(self.iobus) 319 self.malta.ide.pio = self.iobus.master 320 self.malta.ide.config = self.iobus.master --- 21 unchanged lines hidden (view full) --- 342def connectX86ClassicSystem(x86_sys, numCPUs): 343 # Constants similar to x86_traits.hh 344 IO_address_space_base = 0x8000000000000000 345 pci_config_address_space_base = 0xc000000000000000 346 interrupts_address_space_base = 0xa000000000000000 347 APIC_range_size = 1 << 12; 348 349 x86_sys.membus = MemBus() |
350 351 # North Bridge 352 x86_sys.iobus = NoncoherentBus() 353 x86_sys.bridge = Bridge(delay='50ns') 354 x86_sys.bridge.master = x86_sys.iobus.slave 355 x86_sys.bridge.slave = x86_sys.membus.master 356 # Allow the bridge to pass through the IO APIC (two pages), 357 # everything in the IO address range up to the local APIC, and --- 23 unchanged lines hidden (view full) --- 381 x86_sys.pc.attachIO(x86_sys.iobus) 382 383 x86_sys.system_port = x86_sys.membus.slave 384 385def connectX86RubySystem(x86_sys): 386 # North Bridge 387 x86_sys.piobus = NoncoherentBus() 388 |
389 # add the ide to the list of dma devices that later need to attach to 390 # dma controllers 391 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 392 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) 393 394 |
395def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, |
396 Ruby = False): 397 if self == None: 398 self = X86System() 399 400 if not mdesc: 401 # generic system 402 mdesc = SysConfig() 403 self.readfile = mdesc.script() 404 405 self.mem_mode = mem_mode 406 407 # Physical memory |
408 self.mem_ranges = [AddrRange(mdesc.mem())] |
409 410 # Platform 411 self.pc = Pc() 412 413 # Create and connect the busses required by each memory system 414 if Ruby: 415 connectX86RubySystem(self) 416 else: --- 66 unchanged lines hidden (view full) --- 483 base_entries.append(assign_to_apic) 484 assignISAInt(0, 2) 485 assignISAInt(1, 1) 486 for i in range(3, 15): 487 assignISAInt(i, i) 488 self.intel_mp_table.base_entries = base_entries 489 self.intel_mp_table.ext_entries = ext_entries 490 |
491def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, |
492 Ruby = False): 493 self = LinuxX86System() 494 495 # Build up the x86 system and then specialize it for Linux |
496 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) |
497 498 # We assume below that there's at least 1MB of memory. We'll require 2 499 # just to avoid corner cases. |
500 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) |
501 assert(phys_mem_size >= 0x200000) 502 503 self.e820_table.entries = \ 504 [ 505 # Mark the first megabyte of memory as reserved 506 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 507 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 508 # Mark the rest as available --- 33 unchanged lines hidden --- |