1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 60 unchanged lines hidden (view full) --- 69 self.readfile = mdesc.script() 70 self.iobus = NoncoherentBus() 71 self.membus = MemBus() 72 # By default the bridge responds to all addresses above the I/O 73 # base address (including the PCI config space) 74 self.bridge = Bridge(delay='50ns', 75 ranges = [AddrRange(IO_address_space_base, Addr.max)]) 76 self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem())) |
77 self.mem_ranges = [self.physmem.range] |
78 self.bridge.master = self.iobus.slave 79 self.bridge.slave = self.membus.master 80 self.physmem.port = self.membus.master 81 self.disk0 = CowIdeDisk(driveID='master') 82 self.disk2 = CowIdeDisk(driveID='master') 83 self.disk0.childImage(mdesc.disk()) 84 self.disk2.childImage(disk('linux-bigswap2.img')) 85 self.tsunami = BaseTsunami() --- 21 unchanged lines hidden (view full) --- 107def makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 108 class BaseTsunami(Tsunami): 109 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 110 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 111 pci_func=0, pci_dev=0, pci_bus=0) 112 113 physmem = SimpleDRAM(range = AddrRange(mdesc.mem())) 114 self = LinuxAlphaSystem(physmem = physmem) |
115 self.mem_ranges = [self.physmem.range] |
116 if not mdesc: 117 # generic system 118 mdesc = SysConfig() 119 self.readfile = mdesc.script() 120 121 # Create pio bus to connect all device pio ports to rubymem's pio port 122 self.piobus = NoncoherentBus() 123 --- 55 unchanged lines hidden (view full) --- 179 self.bridge = Bridge(delay='50ns') 180 self.t1000 = T1000() 181 self.t1000.attachOnChipIO(self.membus) 182 self.t1000.attachIO(self.iobus) 183 self.physmem = SimpleDRAM(range = AddrRange(Addr('1MB'), size = '64MB'), 184 zero = True) 185 self.physmem2 = SimpleDRAM(range = AddrRange(Addr('2GB'), size ='256MB'), 186 zero = True) |
187 self.mem_ranges = [self.physmem.range, self.physmem2.range] |
188 self.bridge.master = self.iobus.slave 189 self.bridge.slave = self.membus.master 190 self.physmem.port = self.membus.master 191 self.physmem2.port = self.membus.master 192 self.rom.port = self.membus.master 193 self.nvram.port = self.membus.master 194 self.hypervisor_desc.port = self.membus.master 195 self.partition_desc.port = self.membus.master --- 75 unchanged lines hidden (view full) --- 271 except: 272 self.realview.cf_ctrl.disks = [self.cf0] 273 274 if bare_metal: 275 # EOT character on UART will end the simulation 276 self.realview.uart.end_on_eot = True 277 self.physmem = SimpleDRAM(range = AddrRange(Addr(mdesc.mem())), 278 zero = True) |
279 self.mem_ranges = [self.physmem.range] |
280 else: 281 self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 282 self.machine_type = machine_type 283 if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 284 print "The currently selected ARM platforms doesn't support" 285 print " the amount of DRAM you've selected. Please try" 286 print " another platform" 287 sys.exit(1) 288 289 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 290 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 291 292 self.physmem = SimpleDRAM(range = 293 AddrRange(self.realview.mem_start_addr, 294 size = mdesc.mem()), 295 conf_table_reported = True) |
296 self.mem_ranges = [self.physmem.range] |
297 self.realview.setupBootLoader(self.membus, self, binary) 298 self.gic_cpu_addr = self.realview.gic.cpu_addr 299 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 300 301 if mdesc.disk().lower().count('android'): 302 boot_flags += " init=/init " 303 self.boot_osflags = boot_flags 304 --- 19 unchanged lines hidden (view full) --- 324 if not mdesc: 325 # generic system 326 mdesc = SysConfig() 327 self.readfile = mdesc.script() 328 self.iobus = NoncoherentBus() 329 self.membus = MemBus() 330 self.bridge = Bridge(delay='50ns') 331 self.physmem = SimpleDRAM(range = AddrRange('1GB')) |
332 self.mem_ranges = [self.physmem.range] |
333 self.bridge.master = self.iobus.slave 334 self.bridge.slave = self.membus.master 335 self.physmem.port = self.membus.master 336 self.disk0 = CowIdeDisk(driveID='master') 337 self.disk2 = CowIdeDisk(driveID='master') 338 self.disk0.childImage(mdesc.disk()) 339 self.disk2.childImage(disk('linux-bigswap2.img')) 340 self.malta = BaseMalta() --- 89 unchanged lines hidden (view full) --- 430 # generic system 431 mdesc = SysConfig() 432 self.readfile = mdesc.script() 433 434 self.mem_mode = mem_mode 435 436 # Physical memory 437 self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem())) |
438 self.mem_ranges = [self.physmem.range] |
439 440 # Platform 441 self.pc = Pc() 442 443 # Create and connect the busses required by each memory system 444 if Ruby: 445 connectX86RubySystem(self) 446 else: --- 124 unchanged lines hidden --- |