1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 371 unchanged lines hidden (view full) --- 380 AddrRange(IO_address_space_base, 381 interrupts_address_space_base - 1), 382 AddrRange(pci_config_address_space_base, 383 Addr.max) 384 ] 385 386 # Create a bridge from the IO bus to the memory bus to allow access to 387 # the local APIC (two pages) |
388 x86_sys.apicbridge = Bridge(delay='50ns', nack_delay='4ns') 389 x86_sys.apicbridge.slave = x86_sys.iobus.port 390 x86_sys.apicbridge.master = x86_sys.membus.port 391 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 392 interrupts_address_space_base + 393 APIC_range_size - 1)] |
394 395 # connect the io bus 396 x86_sys.pc.attachIO(x86_sys.iobus) 397 398 x86_sys.system_port = x86_sys.membus.port 399 400def connectX86RubySystem(x86_sys): 401 # North Bridge --- 245 unchanged lines hidden --- |