1# Copyright (c) 2006-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 150 unchanged lines hidden (view full) --- 159 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 160 161 return self 162 163def x86IOAddress(port): 164 IO_address_space_base = 0x8000000000000000 165 return IO_address_space_base + port; 166 |
167def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None): |
168 if self == None: 169 self = X86System() 170 171 if not mdesc: 172 # generic system 173 mdesc = SysConfig() 174 mdesc.diskname = 'x86root.img' 175 self.readfile = mdesc.script() --- 22 unchanged lines hidden (view full) --- 198 disk2.childImage(disk('linux-bigswap2.img')) 199 self.pc.south_bridge.ide.disks = [disk0, disk2] 200 201 # Add in a Bios information structure. 202 structures = [X86SMBiosBiosInformation()] 203 self.smbios_table.structures = structures 204 205 # Set up the Intel MP table |
206 for i in xrange(numCPUs): 207 bp = X86IntelMPProcessor( 208 local_apic_id = i, 209 local_apic_version = 0x14, 210 enable = True, 211 bootstrap = (i == 0)) 212 self.intel_mp_table.add_entry(bp) |
213 io_apic = X86IntelMPIOAPIC( |
214 id = numCPUs, |
215 version = 0x11, 216 enable = True, 217 address = 0xfec00000) |
218 self.pc.south_bridge.io_apic.apic_id = io_apic.id |
219 self.intel_mp_table.add_entry(io_apic) 220 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 221 self.intel_mp_table.add_entry(isa_bus) 222 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 223 self.intel_mp_table.add_entry(pci_bus) 224 connect_busses = X86IntelMPBusHierarchy(bus_id=0, 225 subtractive_decode=True, parent_bus=1) 226 self.intel_mp_table.add_entry(connect_busses) 227 pci_dev4_inta = X86IntelMPIOIntAssignment( 228 interrupt_type = 'INT', 229 polarity = 'ConformPolarity', 230 trigger = 'ConformTrigger', 231 source_bus_id = 1, 232 source_bus_irq = 0 + (4 << 2), 233 dest_io_apic_id = io_apic.id, 234 dest_io_apic_intin = 16) 235 self.intel_mp_table.add_entry(pci_dev4_inta); |
236 def assignISAInt(irq, apicPin): 237 assign_8259_to_apic = X86IntelMPIOIntAssignment( 238 interrupt_type = 'ExtInt', 239 polarity = 'ConformPolarity', 240 trigger = 'ConformTrigger', 241 source_bus_id = 0, 242 source_bus_irq = irq, 243 dest_io_apic_id = io_apic.id, 244 dest_io_apic_intin = 0) 245 self.intel_mp_table.add_entry(assign_8259_to_apic) 246 assign_to_apic = X86IntelMPIOIntAssignment( 247 interrupt_type = 'INT', 248 polarity = 'ConformPolarity', 249 trigger = 'ConformTrigger', 250 source_bus_id = 0, 251 source_bus_irq = irq, 252 dest_io_apic_id = io_apic.id, 253 dest_io_apic_intin = apicPin) 254 self.intel_mp_table.add_entry(assign_to_apic) 255 assignISAInt(0, 2) 256 assignISAInt(1, 1) 257 for i in range(3, 15): 258 assignISAInt(i, i) |
259 260 |
261def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None): |
262 self = LinuxX86System() 263 264 # Build up a generic x86 system and then specialize it for Linux |
265 makeX86System(mem_mode, numCPUs, mdesc, self) |
266 267 # We assume below that there's at least 1MB of memory. We'll require 2 268 # just to avoid corner cases. 269 assert(self.physmem.range.second >= 0x200000) 270 271 # Mark the first megabyte of memory as reserved 272 self.e820_table.entries.append(X86E820Entry( 273 addr = 0, --- 98 unchanged lines hidden --- |