1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 174 unchanged lines hidden (view full) --- 183 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 184 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 185 186 if dumpfile: 187 self.etherdump = EtherDump(file=dumpfile) 188 self.etherlink.dump = Parent.etherdump 189 190 return self |
191 192def setMipsOptions(TestCPUClass.CoreParams) 193 #CP0 Configuration 194 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 195 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 196 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 197 TestCPUClass.CoreParams.CP0_PRId_Revision = 0 198 199 #CP0 Interrupt Control 200 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 201 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 202 203 # Config Register 204 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 205 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 206 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 207 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 208 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 209 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 210 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 211 212 #Config 1 Register 213 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 214 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 215 # ***VERY IMPORTANT*** 216 # Remember to modify CP0_Config1 according to cache specs 217 # Examine file ../common/Cache.py 218 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 219 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 220 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 221 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 222 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 223 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 224 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 225 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 226 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 227 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 228 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 229 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 230 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 231 232 #Config 2 Register 233 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 234 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 235 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 236 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 237 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 238 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 239 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 240 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 241 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 242 243 244 #Config 3 Register 245 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 246 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 247 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 248 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 249 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 250 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 251 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 252 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 253 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 254 255 #SRS Ctl - HSS 256 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 257 258 259 #TestCPUClass.CoreParams.tlb = TLB() 260 #TestCPUClass.CoreParams.UnifiedTLB = 1 |