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> IO_address_space_base = 0x80000000000
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< self.bridge = Bridge(delay='50ns', nack_delay='4ns')
---
> # By default the bridge responds to all addresses above the I/O
> # base address (including the PCI config space)
> self.bridge = Bridge(delay='50ns', nack_delay='4ns',
> ranges = [AddrRange(IO_address_space_base, Addr.max)])
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< self.bridge.side_a = self.iobus.port
< self.bridge.side_b = self.membus.port
---
> self.bridge.master = self.iobus.port
> self.bridge.slave = self.membus.port
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> # Constants from iob.cc and uart8250.cc
> iob_man_addr = 0x9800000000
> uart_pio_size = 8
>
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< self.bridge.side_a = self.iobus.port
< self.bridge.side_b = self.membus.port
---
> self.bridge.master = self.iobus.port
> self.bridge.slave = self.membus.port
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>
> # The puart0 and hvuart are placed on the IO bus, so create ranges
> # for them. The remaining IO range is rather fragmented, so poke
> # holes for the iob and partition descriptors etc.
> self.bridge.ranges = \
> [
> AddrRange(self.t1000.puart0.pio_addr,
> self.t1000.puart0.pio_addr + uart_pio_size - 1),
> AddrRange(self.disk0.pio_addr,
> self.t1000.fake_jbi.pio_addr +
> self.t1000.fake_jbi.pio_size - 1),
> AddrRange(self.t1000.fake_clk.pio_addr,
> iob_man_addr - 1),
> AddrRange(self.t1000.fake_l2_1.pio_addr,
> self.t1000.fake_ssi.pio_addr +
> self.t1000.fake_ssi.pio_size - 1),
> AddrRange(self.t1000.hvuart.pio_addr,
> self.t1000.hvuart.pio_addr + uart_pio_size - 1)
> ]
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< self.bridge.side_a = self.iobus.port
< self.bridge.side_b = self.membus.port
---
> self.bridge.master = self.iobus.port
> self.bridge.slave = self.membus.port
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< self.realview.attachOnChipIO(self.membus)
---
> self.realview.attachOnChipIO(self.membus, self.bridge)
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< self.bridge.side_a = self.iobus.port
< self.bridge.side_b = self.membus.port
---
> self.bridge.master = self.iobus.port
> self.bridge.slave = self.membus.port
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> # Constants similar to x86_traits.hh
> IO_address_space_base = 0x8000000000000000
> pci_config_address_space_base = 0xc000000000000000
> interrupts_address_space_base = 0xa000000000000000
> APIC_range_size = 1 << 12;
>
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< x86_sys.bridge.side_a = x86_sys.iobus.port
< x86_sys.bridge.side_b = x86_sys.membus.port
---
> x86_sys.bridge.master = x86_sys.iobus.port
> x86_sys.bridge.slave = x86_sys.membus.port
> # Allow the bridge to pass through the IO APIC (two pages),
> # everything in the IO address range up to the local APIC, and
> # then the entire PCI address space and beyond
> x86_sys.bridge.ranges = \
> [
> AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
> x86_sys.pc.south_bridge.io_apic.pio_addr +
> APIC_range_size - 1),
> AddrRange(IO_address_space_base,
> interrupts_address_space_base - 1),
> AddrRange(pci_config_address_space_base,
> Addr.max)
> ]
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> # Create a bridge from the IO bus to the memory bus to allow access to
> # the local APIC (two pages)
> x86_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns')
> x86_sys.iobridge.slave = x86_sys.iobus.port
> x86_sys.iobridge.master = x86_sys.membus.port
> x86_sys.iobridge.ranges = [AddrRange(interrupts_address_space_base,
> interrupts_address_space_base +
> APIC_range_size - 1)]
>