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< from Util import *
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< def makeLinuxAlphaSystem(cpu, mem_mode, mdesc, icache=None, dcache=None, l2cache=None):
---
> def makeLinuxAlphaSystem(mem_mode, mdesc):
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< self.cpu = cpu
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< connectCpu(self.cpu, self.membus, icache, dcache, l2cache)
< for each_cpu in makeList(self.cpu):
< each_cpu.itb = AlphaITB()
< each_cpu.dtb = AlphaDTB()
< self.cpu.clock = '2GHz'